diff options
| author | Pratyush Anand <pratyush.anand@st.com> | 2014-04-14 15:27:36 +0530 |
|---|---|---|
| committer | Viresh Kumar <viresh.kumar@linaro.org> | 2014-07-14 11:04:43 +0530 |
| commit | 549f3ae1beb187e53f4cec7ee0cbe79b01d27111 (patch) | |
| tree | c0741434bbeefe7fb1a59e4e5f3f35327ea7734e /arch/arm/boot/dts/spear13xx.dtsi | |
| parent | 23b7ad23cb95db188403677c51c997338fb9effd (diff) | |
ARM: SPEAr13xx: Add pcie and miphy DT nodes
This patch adds necessary DT nodes for pcie controllers and miphys for SPEAr13xx
SoCs.
SPEAr1310 has 3 PCIe ports and SPEAr1340 has 1, which are multiplexed with
ahci/sata pins. By default evaluation board of both controller works in ahci
mode. Because of this, these nodes are marked "disabled" by default.
In order to use pcie controller on evaluation boards do necessary modifications
on board and enable (By replacing "disabled" with "okay") pcie and miphy from
respective 'evb' dtsi file.
Phy specific initialization was previously done from spear1340.c, which isn't
required anymore as we have separate drivers for it. Remove it.
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Signed-off-by: Mohit Kumar <mohit.kumar@st.com>
[viresh: fixed logs/cclist/checkpatch warnings, clubbed multiple patches into one]
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Diffstat (limited to 'arch/arm/boot/dts/spear13xx.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/spear13xx.dtsi | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/spear13xx.dtsi b/arch/arm/boot/dts/spear13xx.dtsi index 3a72508c578f..a6eb5436d26d 100644 --- a/arch/arm/boot/dts/spear13xx.dtsi +++ b/arch/arm/boot/dts/spear13xx.dtsi @@ -83,8 +83,8 @@ #size-cells = <1>; compatible = "simple-bus"; ranges = <0x50000000 0x50000000 0x10000000 - 0xb0000000 0xb0000000 0x10000000 - 0xd0000000 0xd0000000 0x02000000 + 0x80000000 0x80000000 0x20000000 + 0xb0000000 0xb0000000 0x22000000 0xd8000000 0xd8000000 0x01000000 0xe0000000 0xe0000000 0x10000000>; |