diff options
| author | Chen-Yu Tsai <wens@csie.org> | 2015-03-26 05:04:48 +0800 |
|---|---|---|
| committer | Maxime Ripard <maxime.ripard@free-electrons.com> | 2015-04-27 08:20:30 +0200 |
| commit | 3a2bc642abee100511021b263032329f94e3a1e4 (patch) | |
| tree | ec985a3581d5231655985757d0e9f1e40231252e /arch/arm/boot/dts/sun6i-a31.dtsi | |
| parent | 59ebbe88a6431d0bd99c792f413ecf69273f2e9d (diff) | |
ARM: dts: sun6i: Add cpu clock reference and operating points to dtsi
The cpu core is clocked from the "cpu" clock. Add a reference to it
in the first cpu node. Also add "cpu0" label to the node.
The operating points were taken from the a list compiled by Maxime Ripard,
which is based on A31 FEX files from the sunxi-boards repository. Not all
boards have the same settings. The settings in this patch are the ones
shared by A/B/C revisions, plus the default clock setting from u-boot.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'arch/arm/boot/dts/sun6i-a31.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/sun6i-a31.dtsi | 14 |
1 files changed, 13 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index 2a37ee93265e..9ea0edb9684c 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -96,10 +96,22 @@ #address-cells = <1>; #size-cells = <0>; - cpu@0 { + cpu0: cpu@0 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <0>; + clocks = <&cpu>; + clock-latency = <244144>; /* 8 32k periods */ + operating-points = < + /* kHz uV */ + 1008000 1200000 + 864000 1200000 + 720000 1100000 + 480000 1000000 + >; + #cooling-cells = <2>; + cooling-min-level = <0>; + cooling-max-level = <3>; }; cpu@1 { |