diff options
| author | Chen-Yu Tsai <wens@csie.org> | 2016-01-21 13:26:38 +0800 |
|---|---|---|
| committer | Maxime Ripard <maxime.ripard@free-electrons.com> | 2016-01-25 00:01:21 +0100 |
| commit | 74124439b93065c35b840f381bb26f61452c18e5 (patch) | |
| tree | dc33b4ce4eb5b7c9de4938de56558d6d84327a1b /arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts | |
| parent | db30fce1eea58e50ae8b2722704b4f529c394dba (diff) | |
ARM: dts: sun8i: sina33: Enable hardware reset and HS-DDR for eMMC
mmc2 has a special pin for eMMC hardware reset, which is controllable
from the controller. Add the "mmc-cap-hw-reset" property to denote that
this controller supports this function, and the pins are actually used.
Also increase the signal drive strength for mmc2 pins, for HS-DDR mode
support.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts')
| -rw-r--r-- | arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts b/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts index 13ce68f06dd6..bd2a3beb4629 100644 --- a/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts +++ b/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts @@ -109,10 +109,13 @@ vmmc-supply = <®_vcc3v0>; bus-width = <8>; non-removable; + cap-mmc-hw-reset; status = "okay"; }; &mmc2_8bit_pins { + /* Increase drive strength for DDR modes */ + allwinner,drive = <SUN4I_PINCTRL_40_MA>; /* eMMC is missing pull-ups */ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; }; |