diff options
| author | Lucas Stach <dev@lynxeye.de> | 2013-01-22 22:46:07 +0100 |
|---|---|---|
| committer | Stephen Warren <swarren@nvidia.com> | 2013-01-28 11:24:09 -0700 |
| commit | ab343e91aa00d6cc1047e8209d610c384ee824b9 (patch) | |
| tree | d8e4ba8a829d4c1b6922ac511de9df27521ccb22 /arch/arm/boot/dts/tegra20-trimslice.dts | |
| parent | c0967ce0a7388fa8818f5529897140f4f7ec8543 (diff) | |
ARM: tegra: move serial clock-frequency attr into the Tegra20 dtsi
No Tegra20 Platform is running PLL_P at another rate than 216MHz, nor is
any using any other PLL as UART source clock. Move attribute into SoC
level dtsi file to slim down board DT files.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'arch/arm/boot/dts/tegra20-trimslice.dts')
| -rw-r--r-- | arch/arm/boot/dts/tegra20-trimslice.dts | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts index 4b6c486ecea5..adf60244ae3c 100644 --- a/arch/arm/boot/dts/tegra20-trimslice.dts +++ b/arch/arm/boot/dts/tegra20-trimslice.dts @@ -263,7 +263,6 @@ serial@70006000 { status = "okay"; - clock-frequency = <216000000>; }; dvi_ddc: i2c@7000c000 { |