diff options
| author | Mark Zhang <markz@nvidia.com> | 2012-10-25 14:52:30 +0800 |
|---|---|---|
| committer | Stephen Warren <swarren@nvidia.com> | 2012-11-15 15:07:28 -0700 |
| commit | cf63346401c61d7910263d2537bb2d8d265156fa (patch) | |
| tree | c2b00239942772ca426207d8b186803dbf6cd037 /arch/arm/boot/dts/tegra20-ventana.dts | |
| parent | 6fb11131ef3400364381661186a55a73b782c3be (diff) | |
ARM: dt: tegra: ventana: define pinmux for ddc
Tegra 2's I2C2 controller can be routed to either the PTA
or DDC pin group on Ventana. So:
- Remove the HDMI function definition of pta pingroup
- Define child i2c adapters(ddc & pta) for I2C2 controller
Signed-off-by: Mark Zhang <markz@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'arch/arm/boot/dts/tegra20-ventana.dts')
| -rw-r--r-- | arch/arm/boot/dts/tegra20-ventana.dts | 69 |
1 files changed, 63 insertions, 6 deletions
diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts index bec8bb297ad8..1dde0d360564 100644 --- a/arch/arm/boot/dts/tegra20-ventana.dts +++ b/arch/arm/boot/dts/tegra20-ventana.dts @@ -64,11 +64,6 @@ nvidia,pins = "dap4"; nvidia,function = "dap4"; }; - ddc { - nvidia,pins = "ddc", "owc", "spdi", "spdo", - "uac"; - nvidia,function = "rsvd2"; - }; dta { nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte"; nvidia,function = "vi"; @@ -98,7 +93,7 @@ nvidia,function = "pcie"; }; hdint { - nvidia,pins = "hdint", "pta"; + nvidia,pins = "hdint"; nvidia,function = "hdmi"; }; i2cp { @@ -129,6 +124,10 @@ "lspi", "lvp1", "lvs"; nvidia,function = "displaya"; }; + owc { + nvidia,pins = "owc", "spdi", "spdo", "uac"; + nvidia,function = "rsvd2"; + }; pmc { nvidia,pins = "pmc"; nvidia,function = "pwr_on"; @@ -248,6 +247,39 @@ nvidia,slew-rate-falling = <3>; }; }; + + state_i2cmux_ddc: pinmux_i2cmux_ddc { + ddc { + nvidia,pins = "ddc"; + nvidia,function = "i2c2"; + }; + pta { + nvidia,pins = "pta"; + nvidia,function = "rsvd4"; + }; + }; + + state_i2cmux_pta: pinmux_i2cmux_pta { + ddc { + nvidia,pins = "ddc"; + nvidia,function = "rsvd4"; + }; + pta { + nvidia,pins = "pta"; + nvidia,function = "i2c2"; + }; + }; + + state_i2cmux_idle: pinmux_i2cmux_idle { + ddc { + nvidia,pins = "ddc"; + nvidia,function = "rsvd4"; + }; + pta { + nvidia,pins = "pta"; + nvidia,function = "rsvd4"; + }; + }; }; i2s@70002800 { @@ -291,6 +323,31 @@ clock-frequency = <400000>; }; + i2cmux { + compatible = "i2c-mux-pinctrl"; + #address-cells = <1>; + #size-cells = <0>; + + i2c-parent = <&{/i2c@7000c400}>; + + pinctrl-names = "ddc", "pta", "idle"; + pinctrl-0 = <&state_i2cmux_ddc>; + pinctrl-1 = <&state_i2cmux_pta>; + pinctrl-2 = <&state_i2cmux_idle>; + + i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + i2c@7000c500 { status = "okay"; clock-frequency = <400000>; |