apalis_t30: apalis-tk1: fix pcie reset for reliable gigabit ethernet operation

It turns out that the current PCIe reset implementation is not quite
working reliably due to some Intel i210 errata. Fix this by making sure
the i210's +V3.3_ETH rail is properly disabled during its reset
sequence.

Also further improve on the bringing up the PCIe switch as found on the
Apalis Evaluation board.

This commit has been further amended to avoid resetting multiple times
due to not differentiating which PCIe port needs resetting. Improve this
by doing specific resets per port only.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Dominik Sliwa <dominik.sliwa@toradex.com>
(downstream commit 7ad9771527d2b1c884beb22d9df28bae899f8d3d)

1 files changed, 0 insertions, 10 deletions

diff --git a/arch/arm/boot/dts/tegra30-apalis-eval.dts b/arch/arm/boot/dts/tegra30-apalis-eval.dts
index 749fc6d1ff70..ca23cacd1412 100644
--- a/arch/arm/boot/dts/tegra30-apalis-eval.dts
+++ b/arch/arm/boot/dts/tegra30-apalis-eval.dts
@@ -236,13 +236,3 @@
 		vin-supply = <&reg_5v0>;
 	};
 };
-
-&gpio {
-	/* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */
-	pex-perst-n {
-		gpio-hog;
-		gpios = <TEGRA_GPIO(S, 7) GPIO_ACTIVE_HIGH>;
-		output-high;
-		line-name = "PEX_PERST_N";
-	};
-};