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authorMasahiro Yamada <yamada.masahiro@socionext.com>2017-08-10 01:43:30 +0900
committerMasahiro Yamada <yamada.masahiro@socionext.com>2017-08-16 01:47:01 +0900
commit69f9cdc63319e5ccc210b30d1cec1dfda7096b04 (patch)
tree87929645679b06441cdc474bb9fd2a02425df4ac /arch/arm/boot/dts/uniphier-pxs2.dtsi
parented8bc76bec988b04b23a452470790bef71426c32 (diff)
ARM: dts: uniphier: add Denali NAND controller node
Add NAND controller node to LD4, Pro4, sLD8, Pro5, and PXs2. Set up pinctrl to enable 2 chip select lines except Pro4. The CS1 for Pro4 is multiplexed with other peripherals such as UART2, so I did not enable it. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Diffstat (limited to 'arch/arm/boot/dts/uniphier-pxs2.dtsi')
-rw-r--r--arch/arm/boot/dts/uniphier-pxs2.dtsi11
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/uniphier-pxs2.dtsi b/arch/arm/boot/dts/uniphier-pxs2.dtsi
index c26d4ba1b9c3..ed2b9a4516aa 100644
--- a/arch/arm/boot/dts/uniphier-pxs2.dtsi
+++ b/arch/arm/boot/dts/uniphier-pxs2.dtsi
@@ -352,6 +352,17 @@
#reset-cells = <1>;
};
};
+
+ nand: nand@68000000 {
+ compatible = "socionext,uniphier-denali-nand-v5b";
+ status = "disabled";
+ reg-names = "nand_data", "denali_reg";
+ reg = <0x68000000 0x20>, <0x68100000 0x1000>;
+ interrupts = <0 65 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_nand2cs>;
+ clocks = <&sys_clk 2>;
+ };
};
};