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| author | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2016-01-06 18:27:27 +0100 |
|---|---|---|
| committer | Max Krummenacher <max.krummenacher@toradex.com> | 2016-03-08 16:13:13 +0100 |
| commit | 408da680a57dfa782b4f70c77616ff765a87823f (patch) | |
| tree | 00e90bcc9b4787ef25a0d1e473c99d0d6dd227a8 /arch/arm/boot/dts/vexpress-v2p-ca5s.dts | |
| parent | b8a2c8165076246e9491e622592da1067dd95196 (diff) | |
PCI: Apalis GEN1 forcing quirk
The Apalis evaluation board needs to set the link speed to 2.5 GT/s
(GEN1). The default link speed setting is 5 GT/s (GEN2). 0x98 is the
Link Control 2 PCIe Capability Register of the PEX8605 PCIe switch.
The switch supports link speed auto negotiation, but falsely sets the
link speed to 5 GT/s.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
Diffstat (limited to 'arch/arm/boot/dts/vexpress-v2p-ca5s.dts')
0 files changed, 0 insertions, 0 deletions