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| author | Zhang Rui <rui.zhang@intel.com> | 2015-06-11 12:52:14 +0800 |
|---|---|---|
| committer | Zhang Rui <rui.zhang@intel.com> | 2015-06-11 12:52:14 +0800 |
| commit | 111b23cf895b5cbcdc1b2c6580be1bb78a577d05 (patch) | |
| tree | 89b840115ccd753216ba0b26e587e52699b99310 /arch/arm/boot/dts/vexpress-v2p-ca9.dts | |
| parent | 6a6bcf08e5d1834447655a762dfaf552b675cc54 (diff) | |
| parent | 53daf9383f34d7bf61358a37449fb4d59fbdafc2 (diff) | |
Merge branches 'release' and 'thermal-soc' of .git into next
Diffstat (limited to 'arch/arm/boot/dts/vexpress-v2p-ca9.dts')
| -rw-r--r-- | arch/arm/boot/dts/vexpress-v2p-ca9.dts | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca9.dts b/arch/arm/boot/dts/vexpress-v2p-ca9.dts index 23662b5a5e9d..d949facba376 100644 --- a/arch/arm/boot/dts/vexpress-v2p-ca9.dts +++ b/arch/arm/boot/dts/vexpress-v2p-ca9.dts @@ -33,28 +33,28 @@ #address-cells = <1>; #size-cells = <0>; - cpu@0 { + A9_0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0>; next-level-cache = <&L2>; }; - cpu@1 { + A9_1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <1>; next-level-cache = <&L2>; }; - cpu@2 { + A9_2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <2>; next-level-cache = <&L2>; }; - cpu@3 { + A9_3: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <3>; @@ -170,6 +170,7 @@ compatible = "arm,pl310-cache"; reg = <0x1e00a000 0x1000>; interrupts = <0 43 4>; + cache-unified; cache-level = <2>; arm,data-latency = <1 1 1>; arm,tag-latency = <1 1 1>; @@ -181,6 +182,8 @@ <0 61 4>, <0 62 4>, <0 63 4>; + interrupt-affinity = <&A9_0>, <&A9_1>, <&A9_2>, <&A9_3>; + }; dcc { |