diff options
| author | Bibek Basu <bbasu@nvidia.com> | 2015-08-04 11:37:07 +0530 |
|---|---|---|
| committer | Matthew Pedro <mapedro@nvidia.com> | 2015-08-05 19:32:42 -0700 |
| commit | 00c31487f7c0b51e03fdff56dc69891568d749cd (patch) | |
| tree | 4130876f3f1a348135b6c7e77b8961d630727b7e /arch/arm/boot | |
| parent | de75d66ce0756cad719d43babd9022a01051a834 (diff) | |
arm: tegra: correct dap2_sclk direction
dap2_sclk direction should be input to
take care of the bidirectional nature of the clk
for codec as master and interface as master
Bug 1643925
Change-Id: Iab4f1a30edd3542fbfc0e1f53dd6ea9f604ed42f
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-on: http://git-master/r/778298
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
Diffstat (limited to 'arch/arm/boot')
| -rw-r--r-- | arch/arm/boot/dts/tegra124-platforms/tegra124-jetson_tk1-pinmux-pm375-0000-c00-00.dtsi | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/boot/dts/tegra124-platforms/tegra124-jetson_tk1-pinmux-pm375-0000-c00-00.dtsi b/arch/arm/boot/dts/tegra124-platforms/tegra124-jetson_tk1-pinmux-pm375-0000-c00-00.dtsi index 2c1ac29abdd1..596facb6e924 100644 --- a/arch/arm/boot/dts/tegra124-platforms/tegra124-jetson_tk1-pinmux-pm375-0000-c00-00.dtsi +++ b/arch/arm/boot/dts/tegra124-platforms/tegra124-jetson_tk1-pinmux-pm375-0000-c00-00.dtsi @@ -30,7 +30,7 @@ nvidia,pins = "dap2_din_pa4"; nvidia,function = "i2s1"; nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_ENABLE>; }; @@ -47,7 +47,7 @@ nvidia,function = "i2s1"; nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; }; dap2_sclk_pa3 { @@ -55,7 +55,7 @@ nvidia,function = "i2s1"; nvidia,pull = <TEGRA_PIN_PULL_NONE>; nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; }; dvfs_pwm_px0 { |