diff options
| author | Max Krummenacher <max.krummenacher@toradex.com> | 2014-09-18 20:29:12 +0200 |
|---|---|---|
| committer | Max Krummenacher <max.krummenacher@toradex.com> | 2014-09-18 20:56:15 +0200 |
| commit | f1aaf3934fdb9b572d24cf5ddf887e0b9f19ac5b (patch) | |
| tree | ccfd75e9a864ea84763bb02cc3d5badd0995ed2b /arch/arm/boot | |
| parent | fe20bd70491b689514dd1032121dd5acd6b7eacd (diff) | |
Colibri iMX6 dtb: enable the buffers for RDnWR, nPWE
This enables the buffers which bring the WE# signal to SODIMM-93/99
and tri-states the CPU pins directly connected to SODIMM-93/99.
Diffstat (limited to 'arch/arm/boot')
| -rw-r--r-- | arch/arm/boot/dts/imx6qdl-colibri.dtsi | 16 |
1 files changed, 15 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/imx6qdl-colibri.dtsi b/arch/arm/boot/dts/imx6qdl-colibri.dtsi index 4b269547d8bf..6000f152bd9e 100644 --- a/arch/arm/boot/dts/imx6qdl-colibri.dtsi +++ b/arch/arm/boot/dts/imx6qdl-colibri.dtsi @@ -470,6 +470,19 @@ MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1 >; }; + pinctrl_weim_rdnwr_1: weim_rdnwr-1 { + fsl,pins = < + MX6QDL_PAD_SD2_CLK__GPIO1_IO10 PAD_CTRL_IN + MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 PAD_CTRL_HYS_PD + >; + }; + pinctrl_weim_npwe_1: weim_npwe-1 { + fsl,pins = < + MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 PAD_CTRL_IN + MX6QDL_PAD_RGMII_TD2__GPIO6_IO22 PAD_CTRL_HYS_PD + >; + }; + /* ADDRESS[16:18] [25] used as GPIO */ pinctrl_weim_gpio_1: weim_gpio-1 { fsl,pins = < @@ -643,7 +656,8 @@ &weim { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_weim_sram_1 &pinctrl_weim_cs0_1 - &pinctrl_weim_cs1_1 &pinctrl_weim_cs2_1>; + &pinctrl_weim_cs1_1 &pinctrl_weim_cs2_1 + &pinctrl_weim_rdnwr_1 &pinctrl_weim_npwe_1>; #address-cells = <2>; #size-cells = <1>; status = "disabled"; |