diff options
author | Catalin Marinas <catalin.marinas@arm.com> | 2009-06-23 18:16:03 +0100 |
---|---|---|
committer | Catalin Marinas <catalin.marinas@arm.com> | 2009-09-08 13:19:43 +0100 |
commit | 053d9d0f117f5b3112eb17f2224b36447abbdc5c (patch) | |
tree | b54b0a8f33e2b506bf14a8b35c6d56829b722876 /arch/arm/include/asm/ptrace.h | |
parent | 7860173c5e251e9be14d33873ad769d314180df7 (diff) |
Cortex-M3: Add base support for Cortex-M3
This patch adds the base support for the Cortex-M3 processor (ARMv7-M
architecture). It consists of the corresponding arch/arm/mm/ files and
various #ifdef's around the kernel. Exception handling is implemented by
a subsequent patch.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm/include/asm/ptrace.h')
-rw-r--r-- | arch/arm/include/asm/ptrace.h | 38 |
1 files changed, 37 insertions, 1 deletions
diff --git a/arch/arm/include/asm/ptrace.h b/arch/arm/include/asm/ptrace.h index bbecccda76d0..1f7419c9fcc0 100644 --- a/arch/arm/include/asm/ptrace.h +++ b/arch/arm/include/asm/ptrace.h @@ -37,16 +37,25 @@ #define FIQ26_MODE 0x00000001 #define IRQ26_MODE 0x00000002 #define SVC26_MODE 0x00000003 +#ifndef CONFIG_CPU_V7M #define USR_MODE 0x00000010 +#define SVC_MODE 0x00000013 +#else +#define USR_MODE 0x00000000 +#define SVC_MODE 0x00000000 +#endif #define FIQ_MODE 0x00000011 #define IRQ_MODE 0x00000012 -#define SVC_MODE 0x00000013 #define ABT_MODE 0x00000017 #define UND_MODE 0x0000001b #define SYSTEM_MODE 0x0000001f #define MODE32_BIT 0x00000010 #define MODE_MASK 0x0000001f +#ifndef CONFIG_CPU_V7M #define PSR_T_BIT 0x00000020 +#else +#define PSR_T_BIT 0x01000000 +#endif #define PSR_F_BIT 0x00000040 #define PSR_I_BIT 0x00000080 #define PSR_A_BIT 0x00000100 @@ -101,6 +110,28 @@ struct pt_regs { long uregs[18]; }; +#ifdef CONFIG_CPU_V7M +/* Automatically saved registers */ +#define ARM_cpsr uregs[17] +#define ARM_pc uregs[16] +#define ARM_lr uregs[15] +#define ARM_ip uregs[14] +#define ARM_r3 uregs[13] +#define ARM_r2 uregs[12] +#define ARM_r1 uregs[11] +#define ARM_r0 uregs[10] +/* saved by the exception entry code */ +#define ARM_EXC_lr uregs[9] +#define ARM_sp uregs[8] +#define ARM_fp uregs[7] +#define ARM_r10 uregs[6] +#define ARM_r9 uregs[5] +#define ARM_r8 uregs[4] +#define ARM_r7 uregs[3] +#define ARM_r6 uregs[2] +#define ARM_r5 uregs[1] +#define ARM_r4 uregs[0] +#else #define ARM_cpsr uregs[16] #define ARM_pc uregs[15] #define ARM_lr uregs[14] @@ -119,6 +150,7 @@ struct pt_regs { #define ARM_r1 uregs[1] #define ARM_r0 uregs[0] #define ARM_ORIG_r0 uregs[17] +#endif #ifdef __KERNEL__ @@ -150,6 +182,7 @@ struct pt_regs { */ static inline int valid_user_regs(struct pt_regs *regs) { +#ifndef CONFIG_CPU_V7M if (user_mode(regs) && (regs->ARM_cpsr & PSR_I_BIT) == 0) { regs->ARM_cpsr &= ~(PSR_F_BIT | PSR_A_BIT); return 1; @@ -163,6 +196,9 @@ static inline int valid_user_regs(struct pt_regs *regs) regs->ARM_cpsr |= USR_MODE; return 0; +#else + return 1; +#endif } #define instruction_pointer(regs) (regs)->ARM_pc |