diff options
| author | Krzysztof Hałasa <khalasa@piap.pl> | 2014-09-16 12:37:16 +0200 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2014-09-25 23:35:01 +0200 |
| commit | 367dc4b75f4349d5363bc3ebdc030939db944786 (patch) | |
| tree | 22d640b9c8e104bba156f4f7371c92848fd35bc5 /arch/arm/mach-cns3xxx | |
| parent | defaa4d1dc97320ccc0ea83bc3851443b1c9083a (diff) | |
CNS3xxx: Fix PCIe read size limit.
Max_Read_Request_Size is 3 bits wide, not 2 bits.
Also fix the message.
Signed-off-by: Krzysztof Hałasa <khalasa@piap.pl>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/mach-cns3xxx')
| -rw-r--r-- | arch/arm/mach-cns3xxx/pcie.c | 15 |
1 files changed, 9 insertions, 6 deletions
diff --git a/arch/arm/mach-cns3xxx/pcie.c b/arch/arm/mach-cns3xxx/pcie.c index fbfe852286e8..45d6bd09e6ef 100644 --- a/arch/arm/mach-cns3xxx/pcie.c +++ b/arch/arm/mach-cns3xxx/pcie.c @@ -299,12 +299,15 @@ static void __init cns3xxx_pcie_hw_init(struct cns3xxx_pcie *cnspci) devfn = PCI_DEVFN(0, 0); pos = pci_bus_find_capability(&bus, devfn, PCI_CAP_ID_EXP); pci_bus_read_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, &dc); - dc &= ~(0x3 << 12); /* Clear Device Control Register [14:12] */ - pci_bus_write_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, dc); - pci_bus_read_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, &dc); - if (!(dc & (0x3 << 12))) - pr_info("PCIe: Set Device Max_Read_Request_Size to 128 byte\n"); - + if (dc & PCI_EXP_DEVCTL_READRQ) { + dc &= ~PCI_EXP_DEVCTL_READRQ; + pci_bus_write_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, dc); + pci_bus_read_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, &dc); + if (dc & PCI_EXP_DEVCTL_READRQ) + pr_warn("PCIe: Unable to set device Max_Read_Request_Size\n"); + else + pr_info("PCIe: Max_Read_Request_Size set to 128 bytes\n"); + } /* Disable PCIe0 Interrupt Mask INTA to INTD */ __raw_writel(~0x3FFF, MISC_PCIE_INT_MASK(port)); } |