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authorWill Deacon <will.deacon@arm.com>2011-02-21 14:37:43 +0000
committerWill Deacon <will.deacon@arm.com>2011-05-11 16:04:15 +0100
commit0f43563f2d9d8f6f9e0727e4eedb7f557ed2fb4c (patch)
tree63629b8ef5a596ba0eb25ecac614ed1b8978850e /arch/arm/mach-exynos4
parentee144182590a6bd9ed1481cb09d15b92e6b5c348 (diff)
ARM: s5pv310: update IRQ combiner to use chained entry/exit functions
This patch updates the IRQ combiner chained IRQ handler code to use the chained IRQ enter/exit functions in order to function correctly on primary controllers with different methods of flow control. This is required for the GIC to move to fasteoi interrupt handling. Cc: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'arch/arm/mach-exynos4')
-rw-r--r--arch/arm/mach-exynos4/irq-combiner.c6
1 files changed, 2 insertions, 4 deletions
diff --git a/arch/arm/mach-exynos4/irq-combiner.c b/arch/arm/mach-exynos4/irq-combiner.c
index f488b66d6806..5a2758ab055e 100644
--- a/arch/arm/mach-exynos4/irq-combiner.c
+++ b/arch/arm/mach-exynos4/irq-combiner.c
@@ -59,8 +59,7 @@ static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
unsigned int cascade_irq, combiner_irq;
unsigned long status;
- /* primary controller ack'ing */
- chip->irq_ack(&desc->irq_data);
+ chained_irq_enter(chip, desc);
spin_lock(&irq_controller_lock);
status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
@@ -79,8 +78,7 @@ static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
generic_handle_irq(cascade_irq);
out:
- /* primary controller unmasking */
- chip->irq_unmask(&desc->irq_data);
+ chained_irq_exit(chip, desc);
}
static struct irq_chip combiner_chip = {