diff options
| author | Ranjani Vaidyanathan <ra5478@freescale.com> | 2013-11-05 14:44:20 -0600 |
|---|---|---|
| committer | Nitin Garg <nitin.garg@freescale.com> | 2014-08-27 18:06:24 -0500 |
| commit | 5e6e550c67d353c07ce33369fc0c1f92c554e9f0 (patch) | |
| tree | 3fa28b3d8ccd46a68cbadca65ccd4f46af07ec44 /arch/arm/mach-imx/busfreq-imx6.c | |
| parent | 90e6a9a83f47b98d4b262aa34aa516b4bbc75947 (diff) | |
ENGR00286345 [iMX6DL] Fixed random hang bug in bus freq driver
Incorrect clock disable of PLL2 caused random hangs during
DDR freq change in iMX6DL.
Remove PERCLK freq change code as this is not required for TO1.1
and later.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
Diffstat (limited to 'arch/arm/mach-imx/busfreq-imx6.c')
| -rw-r--r-- | arch/arm/mach-imx/busfreq-imx6.c | 10 |
1 files changed, 4 insertions, 6 deletions
diff --git a/arch/arm/mach-imx/busfreq-imx6.c b/arch/arm/mach-imx/busfreq-imx6.c index a32b1d25fbc1..bc9265293477 100644 --- a/arch/arm/mach-imx/busfreq-imx6.c +++ b/arch/arm/mach-imx/busfreq-imx6.c @@ -48,7 +48,8 @@ #include "hardware.h" #define LPAPM_CLK 24000000 -#define DDR_AUDIO_CLK 100000000 +#define DDR3_AUDIO_CLK 50000000 +#define LPDDR2_AUDIO_CLK 100000000 int high_bus_freq_mode; int med_bus_freq_mode; @@ -114,7 +115,7 @@ static void enter_lpm_imx6sl(void) if (audio_bus_count) { /* Set up DDR to 100MHz. */ spin_lock_irqsave(&freq_lock, flags); - update_lpddr2_freq(DDR_AUDIO_CLK); + update_lpddr2_freq(LPDDR2_AUDIO_CLK); spin_unlock_irqrestore(&freq_lock, flags); /* Fix the clock tree in kernel */ @@ -245,7 +246,7 @@ int reduce_bus_freq(void) if (audio_bus_count) { /* Need to ensure that PLL2_PFD_400M is kept ON. */ clk_prepare_enable(pll2_400); - update_ddr_freq(DDR_AUDIO_CLK); + update_ddr_freq(DDR3_AUDIO_CLK); /* Make sure periph clk's parent also got updated */ ret = clk_set_parent(periph_clk2_sel, pll3); if (ret) @@ -283,9 +284,6 @@ int reduce_bus_freq(void) low_bus_freq_mode = 1; audio_bus_freq_mode = 0; } - if (high_bus_freq_mode && cpu_is_imx6dl()) - clk_disable_unprepare(pll2_400); - } clk_disable_unprepare(pll3); |