summaryrefslogtreecommitdiff
path: root/arch/arm/mach-imx/clk-imx6sl.c
diff options
context:
space:
mode:
authorNicolin Chen <Guangyu.Chen@freescale.com>2014-04-23 12:42:45 +0800
committerNicolin Chen <Guangyu.Chen@freescale.com>2014-04-23 16:48:23 +0800
commitf12e2ea9c6c5557adb3bbe26c51021978f2c8d99 (patch)
tree5b1989f25745aa10f70717f0ac654b023f1c1075 /arch/arm/mach-imx/clk-imx6sl.c
parentb50eb55b1eb35e8e568ab777dc794370f20464eb (diff)
ENGR00309977-2 ARM: imx6q/sl: Set SPDIF clock to 22736841Hz
Since we no longer use clk_set_rate() in spdif driver, the rate we provide to it on imx6q/sl platforms is no more contented for its supporting sample rates. By setting the clock to 22736841Hz, we can get the sample rates: 48008Hz for 48000Hz 32005Hz for 32000Hz 43859Hz for 44100Hz The results for 48KHz and 32KHz has changed comparing to the previous release, but the one for 44100Hz has a bit lose even though it should be the best we can get based on the current clock rate. If user want to playback a perfect 44100Hz, they need to change the parent clock rate. Acked-by: Wang Shengjiu <b02247@freescale.com> Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
Diffstat (limited to 'arch/arm/mach-imx/clk-imx6sl.c')
-rw-r--r--arch/arm/mach-imx/clk-imx6sl.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm/mach-imx/clk-imx6sl.c b/arch/arm/mach-imx/clk-imx6sl.c
index 95f8b0b8d029..c9eb48a09159 100644
--- a/arch/arm/mach-imx/clk-imx6sl.c
+++ b/arch/arm/mach-imx/clk-imx6sl.c
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ * Copyright (C) 2013-2014 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@@ -458,6 +458,7 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
/* Audio clocks */
clk_set_parent(clks[IMX6SL_CLK_SPDIF0_SEL], clks[IMX6SL_CLK_PLL3_PFD3]);
+ clk_set_rate(clks[IMX6SL_CLK_SPDIF0_PODF], 227368421);
/* set extern_audio to be sourced from PLL4/audio PLL */
clk_set_parent(clks[IMX6SL_CLK_EXTERN_AUDIO_SEL], clks[IMX6SL_CLK_PLL4_AUDIO_DIV]);