diff options
author | Arnd Bergmann <arnd@arndb.de> | 2012-01-09 16:01:00 +0000 |
---|---|---|
committer | Arnd Bergmann <arnd@arndb.de> | 2012-01-09 16:01:00 +0000 |
commit | a07613a54d700a974f3a4a657da78ef5d097315d (patch) | |
tree | e4bc91713e02fa6d8f08b07de53ea8f905593dfa /arch/arm/mach-imx/clock-imx35.c | |
parent | 65db039bf7402f0a5b19cbf6dcff55ebea433b8b (diff) | |
parent | 928a11ba36f999436915ea2b1eadf54301f93059 (diff) |
Merge branch 'samsung/dt' into samsung/cleanup
Conflicts:
arch/arm/mach-s3c64xx/Makefile
arch/arm/mach-s5pc100/Makefile
arch/arm/mach-s5pv210/Makefile
Pull in previously resolved conflicts:
The Makefiles were reorganized in the "rmk/restart" series and modified
in the "samsung/cleanup series". This also pulls in the other conflict
resolutions from the restart series against the samsung/dt series.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/mach-imx/clock-imx35.c')
-rw-r--r-- | arch/arm/mach-imx/clock-imx35.c | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/arch/arm/mach-imx/clock-imx35.c b/arch/arm/mach-imx/clock-imx35.c index 8116f119517d..ac8238caecb9 100644 --- a/arch/arm/mach-imx/clock-imx35.c +++ b/arch/arm/mach-imx/clock-imx35.c @@ -507,7 +507,7 @@ static struct clk_lookup lookups[] = { int __init mx35_clocks_init() { - unsigned int cgr2 = 3 << 26, cgr3 = 0; + unsigned int cgr2 = 3 << 26; #if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_ICEDCC) cgr2 |= 3 << 16; @@ -521,6 +521,12 @@ int __init mx35_clocks_init() __raw_writel((3 << 18), CCM_BASE + CCM_CGR0); __raw_writel((3 << 2) | (3 << 4) | (3 << 6) | (3 << 8) | (3 << 16), CCM_BASE + CCM_CGR1); + __raw_writel(cgr2, CCM_BASE + CCM_CGR2); + __raw_writel(0, CCM_BASE + CCM_CGR3); + + clk_enable(&iim_clk); + imx_print_silicon_rev("i.MX35", mx35_revision()); + clk_disable(&iim_clk); /* * Check if we came up in internal boot mode. If yes, we need some @@ -529,17 +535,11 @@ int __init mx35_clocks_init() */ if (!(__raw_readl(CCM_BASE + CCM_RCSR) & (3 << 10))) { /* Additionally turn on UART1, SCC, and IIM clocks */ - cgr2 |= 3 << 16 | 3 << 4; - cgr3 |= 3 << 2; + clk_enable(&iim_clk); + clk_enable(&uart1_clk); + clk_enable(&scc_clk); } - __raw_writel(cgr2, CCM_BASE + CCM_CGR2); - __raw_writel(cgr3, CCM_BASE + CCM_CGR3); - - clk_enable(&iim_clk); - imx_print_silicon_rev("i.MX35", mx35_revision()); - clk_disable(&iim_clk); - #ifdef CONFIG_MXC_USE_EPIT epit_timer_init(&epit1_clk, MX35_IO_ADDRESS(MX35_EPIT1_BASE_ADDR), MX35_INT_EPIT1); |