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authorBai Ping <ping.bai@nxp.com>2016-10-14 12:49:08 +0800
committerRobby Cai <robby.cai@nxp.com>2016-11-16 15:54:16 +0800
commit9ab4fc1cb2ece23e714c0ade5099b71834131eca (patch)
treefcf3631a79276c6f11bf5ef5a02c7b0b84a79fc7 /arch/arm/mach-imx/common.c
parent44fe4e2ad4fc019602ae69bf879f8fcdcfa3ed79 (diff)
MLK-13344-04 ARM: imx: Add busfreq support on imx6sll
Add bufreq driver support on i.MX6SLL. For i.MX6SLL, it only support LPDDR2 and LPDDR3. the DDR clock change flow is same on these two type of DDR. Signed-off-by: Bai Ping <ping.bai@nxp.com> (cherry picked from commit 8479afb4e7c52c6de1bedefb00a7cea4320fc14d)
Diffstat (limited to 'arch/arm/mach-imx/common.c')
-rw-r--r--arch/arm/mach-imx/common.c6
1 files changed, 5 insertions, 1 deletions
diff --git a/arch/arm/mach-imx/common.c b/arch/arm/mach-imx/common.c
index c53f9c477d0d..3016f60ce141 100644
--- a/arch/arm/mach-imx/common.c
+++ b/arch/arm/mach-imx/common.c
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
@@ -132,6 +132,10 @@ u32 imx6_lpddr2_freq_change_start, imx6_lpddr2_freq_change_end;
void mx6_lpddr2_freq_change(u32 freq, int bus_freq_mode) {}
#endif
+#if !defined(CONFIG_SOC_IMX6SL)
+void imx6sll_lpddr2_freq_change(u32 freq, int bus_freq_mode) {}
+#endif
+
#if !defined(CONFIG_SOC_IMX6SX) && !defined(CONFIG_SOC_IMX6UL)
u32 imx6_up_ddr3_freq_change_start, imx6_up_ddr3_freq_change_end;
struct imx6_busfreq_info {