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authorAnson Huang <b20788@freescale.com>2015-08-12 14:18:37 +0800
committerLeonard Crestez <leonard.crestez@nxp.com>2018-08-23 16:57:07 +0300
commitbbc6fecd0c91687df475269359a3910a876dc5ee (patch)
tree03e541f5d2fac777cf21714f8efc4433931c67c3 /arch/arm/mach-imx/cpuidle.h
parent8353ed5e7a43f56047d9f0fae0e2dd3002bae56a (diff)
MLK-11357-2 ARM: imx: add cpuidle support for imx7d
Enable cpuidle for i.MX7D, total 3 level idle supported: 1. ARM WFI; 2. WAIT mode; 3. Low power idle with ARM/SCU platform power off. Only when system in low bus freq mode, system is able to enter low power idle, and only when both of 2 cores are in low power idle, ARM/SCU platform will be powered off. DDR will be put into low power mode when low power idle is entered. Signed-off-by: Anson Huang <b20788@freescale.com>
Diffstat (limited to 'arch/arm/mach-imx/cpuidle.h')
-rw-r--r--arch/arm/mach-imx/cpuidle.h7
1 files changed, 6 insertions, 1 deletions
diff --git a/arch/arm/mach-imx/cpuidle.h b/arch/arm/mach-imx/cpuidle.h
index f9140128ba05..6106fc9a0cd9 100644
--- a/arch/arm/mach-imx/cpuidle.h
+++ b/arch/arm/mach-imx/cpuidle.h
@@ -1,5 +1,5 @@
/*
- * Copyright 2012 Freescale Semiconductor, Inc.
+ * Copyright 2012-2015 Freescale Semiconductor, Inc.
* Copyright 2012 Linaro Ltd.
*
* The code contained herein is licensed under the GNU General Public
@@ -15,6 +15,7 @@ extern int imx5_cpuidle_init(void);
extern int imx6q_cpuidle_init(void);
extern int imx6sl_cpuidle_init(void);
extern int imx6sx_cpuidle_init(void);
+extern int imx7d_cpuidle_init(void);
#else
static inline int imx5_cpuidle_init(void)
{
@@ -32,4 +33,8 @@ static inline int imx6sx_cpuidle_init(void)
{
return 0;
}
+static inline int imx7d_cpuidle_init(void)
+{
+ return 0;
+}
#endif