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| author | Arnd Bergmann <arnd@arndb.de> | 2016-03-02 23:30:17 +0100 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2016-03-02 23:30:17 +0100 |
| commit | f3a186fbfd413f2453c511da2dbcdc594c87dbde (patch) | |
| tree | 7a35123458eb9904f8027c3bc15057e607707c2d /arch/arm/mach-imx/mach-imx51.c | |
| parent | e91fb3bd757569aca48785358a4adbf41334d382 (diff) | |
| parent | d2443b2e6167e80eca9a068d5ecc0e6f081b3ca4 (diff) | |
Merge tag 'imx-soc-4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/soc
Merge "i.MX SoC update for 4.6" from Shawn Guo:
- Enable big endian mode support for i.MX platform
- Add support for i.MX6QP SoC which is the latest i.MX6 family addition
- Add basic suspend/resume support for i.MX25
- A couple of i.MX7D support updates
- A few random code cleanups
* tag 'imx-soc-4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
ARM: imx: Make reset_control_ops const
ARM: imx: Do L2 errata only if the L2 cache isn't enabled
ARM: imx: select ARM_CPU_SUSPEND only for imx6
ARM: mx25: Add basic suspend/resume support
ARM: imx: Add msl code support for imx6qp
ARM: imx: enable big endian mode
ARM: imx: use endian-safe readl/readw/writel/writew
ARM: imx7d: correct chip version information
ARM: imx: select HAVE_ARM_ARCH_TIMER if selected i.MX7D
ARM: imx6: fix cleanup path in imx6q_suspend_init()
Diffstat (limited to 'arch/arm/mach-imx/mach-imx51.c')
| -rw-r--r-- | arch/arm/mach-imx/mach-imx51.c | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/arch/arm/mach-imx/mach-imx51.c b/arch/arm/mach-imx/mach-imx51.c index b015129e4045..6883fbaf9484 100644 --- a/arch/arm/mach-imx/mach-imx51.c +++ b/arch/arm/mach-imx/mach-imx51.c @@ -40,11 +40,10 @@ static void __init imx51_ipu_mipi_setup(void) WARN_ON(!hsc_addr); /* setup MIPI module to legacy mode */ - __raw_writel(0xf00, hsc_addr); + imx_writel(0xf00, hsc_addr); /* CSI mode: reserved; DI control mode: legacy (from Freescale BSP) */ - __raw_writel(__raw_readl(hsc_addr + 0x800) | 0x30ff, - hsc_addr + 0x800); + imx_writel(imx_readl(hsc_addr + 0x800) | 0x30ff, hsc_addr + 0x800); iounmap(hsc_addr); } |