diff options
| author | Anson Huang <Anson.Huang@nxp.com> | 2016-11-21 21:00:05 +0800 |
|---|---|---|
| committer | Leonard Crestez <leonard.crestez@nxp.com> | 2018-08-24 12:41:33 +0300 |
| commit | 74af0de94fceb69ab28b810f4e55987ae0d6fddd (patch) | |
| tree | 34c94701ebe664d1a9d9f065d0407d3ff5cdcc6c /arch/arm/mach-imx/mx7ulp.h | |
| parent | c938d31d665589ff50a13e9af41a8873c17319c1 (diff) | |
MLK-13487-2 ARM: imx: add NVCC_DRAM_SW control for i.mx7ulp
When enter VLLS mode, DRAM is in self-refresh, NVCC_DRAM_SW
can be off to save power.
As the static io-map formula is no longer feasible on i.MX7ULP,
here we change it to ioremap for creating iram tlb.
Remove the physical module base address in pm_info structure
to save iram space.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Diffstat (limited to 'arch/arm/mach-imx/mx7ulp.h')
| -rw-r--r-- | arch/arm/mach-imx/mx7ulp.h | 20 |
1 files changed, 16 insertions, 4 deletions
diff --git a/arch/arm/mach-imx/mx7ulp.h b/arch/arm/mach-imx/mx7ulp.h index de4f1e0a8f16..a5f9bb272d14 100644 --- a/arch/arm/mach-imx/mx7ulp.h +++ b/arch/arm/mach-imx/mx7ulp.h @@ -14,22 +14,34 @@ #define MX7ULP_IO_P2V(x) IMX_IO_P2V(x) #define MX7ULP_IO_ADDRESS(x) IOMEM(MX7ULP_IO_P2V(x)) -#define MX7ULP_AIPS1_BASE_ADDR 0x40300000 +#define MX7ULP_AIPS1_BASE_ADDR 0x40000000 #define MX7ULP_AIPS1_SIZE 0x100000 -#define MX7ULP_AIPS2_BASE_ADDR 0x40a00000 -#define MX7ULP_AIPS2_SIZE 0x400000 -#define MX7ULP_AIPS3_BASE_ADDR 0x41000000 +#define MX7ULP_AIPS2_BASE_ADDR 0x40300000 +#define MX7ULP_AIPS2_SIZE 0x100000 +#define MX7ULP_AIPS3_BASE_ADDR 0x40400000 #define MX7ULP_AIPS3_SIZE 0x100000 +#define MX7ULP_AIPS4_BASE_ADDR 0x40a00000 +#define MX7ULP_AIPS4_SIZE 0x100000 +#define MX7ULP_AIPS5_BASE_ADDR 0x41000000 +#define MX7ULP_AIPS5_SIZE 0x100000 +#define MX7ULP_GPIOC_BASE_ADDR 0x400f0000 +#define MX7ULP_GPIOC_SIZE 0x1000 #define MX7ULP_PCC3_BASE_ADDR 0x40b30000 #define MX7ULP_PCC3_SIZE 0x1000 #define MX7ULP_SCG1_BASE_ADDR 0x403e0000 #define MX7ULP_SCG1_SIZE 0x1000 +#define MX7ULP_PCC2_BASE_ADDR 0x403f0000 +#define MX7ULP_PCC2_SIZE 0x1000 #define MX7ULP_SIM_BASE_ADDR 0x410a3000 #define MX7ULP_SIM_SIZE 0x1000 #define MX7ULP_PMC1_BASE_ADDR 0x40400000 #define MX7ULP_PMC1_SIZE 0x1000 +#define MX7ULP_SMC1_BASE_ADDR 0x40410000 +#define MX7ULP_SMC1_SIZE 0x1000 #define MX7ULP_MMDC_BASE_ADDR 0x40ab0000 #define MX7ULP_MMDC_SIZE 0x1000 +#define MX7ULP_IOMUXC1_BASE_ADDR 0x40ac0000 +#define MX7ULP_IOMUXC1_BASE__SIZE 0x1000 #define MX7ULP_MMDC_IO_BASE_ADDR 0x40ad0000 #define MX7ULP_MMDC_IO_SIZE 0x1000 |