diff options
| author | Bai Ping <ping.bai@nxp.com> | 2017-06-09 18:10:35 +0800 |
|---|---|---|
| committer | Jason Liu <jason.hui.liu@nxp.com> | 2019-02-12 10:26:46 +0800 |
| commit | 30c33158f7db24a4c421db7e30f1ad7cebe1e95f (patch) | |
| tree | 0040cc73fcb3bd727af3266a4ab6fa2ab0f174c4 /arch/arm/mach-imx/mx7ulp.h | |
| parent | 50d8740c428918b90252a3649db104ed239c840d (diff) | |
MLK-15056 arm: imx: use static mapping for imx7ulp AIPSx memory space
The AIPSx address space of i.MX7ULP need to be mapped as SZ_1M block
in iRAM tlb for suspend code use. If we use ioremap to map these
address region into kernel space, we can't make sure that the returned
virtual address is 1M alignment. So we can map this address regions
as static, then if we use the ioremap to map these memory regions, it will
always return the virtual address of static mapping. So we can make sure
the virtual address is 1M aligned.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Diffstat (limited to 'arch/arm/mach-imx/mx7ulp.h')
| -rw-r--r-- | arch/arm/mach-imx/mx7ulp.h | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/mx7ulp.h b/arch/arm/mach-imx/mx7ulp.h index a5f9bb272d14..a00e86f27e65 100644 --- a/arch/arm/mach-imx/mx7ulp.h +++ b/arch/arm/mach-imx/mx7ulp.h @@ -1,5 +1,6 @@ /* * Copyright (C) 2016 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright NXP 2017. */ /* @@ -45,6 +46,16 @@ #define MX7ULP_MMDC_IO_BASE_ADDR 0x40ad0000 #define MX7ULP_MMDC_IO_SIZE 0x1000 +/* below is just used for static mapping of the AIPSx's memory region */ +#define MX7ULP_AIPS_VIRT_BASE(x) (0xf4000000 + ((x) * SZ_1M)) + +#define mx7ulp_aips_map_entry(index, _type) { \ + .virtual = MX7ULP_AIPS_VIRT_BASE(index), \ + .pfn = __phys_to_pfn(MX7ULP_AIPS ## index ## _BASE_ADDR), \ + .length = SZ_1M, \ + .type = _type, \ +} + #define TT_ATTRIB_NON_CACHEABLE_1M 0x802 #define MX7ULP_IRAM_TLB_SIZE 0x4000 #define MX7ULP_SUSPEND_OCRAM_SIZE 0x1000 |