diff options
| author | Anson Huang <Anson.Huang@nxp.com> | 2016-10-13 04:59:34 +0800 |
|---|---|---|
| committer | Jason Liu <jason.hui.liu@nxp.com> | 2019-02-12 10:25:02 +0800 |
| commit | 7aa6891fdbf8bca71b1b7d6315cafe1962b2c24f (patch) | |
| tree | a1e81d1504d43b151402457d7715b3dfef0dda5d /arch/arm/mach-imx/pm-imx6.c | |
| parent | f869348354cd1b7dbe36a3ed043d186c24b81898 (diff) | |
MLK-13333-1 ARM: imx: correct i.mx6sll dram io low power mode
i.MX6SLL has different DRAM IO offset, and it has no
CAS/RAS/ODT/RESET pin now, correct the DRAM IO offset.
To better support all different i.MX6 SoCs and different
DRAM types, introduce a new column to store the low power
settings for DRAM IO, then suspend asm code no need to check
SoC or DRAM type, just get the DRAM IO's low power
settings from OCRAM pm_info and set to each DRAM IO.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Diffstat (limited to 'arch/arm/mach-imx/pm-imx6.c')
| -rw-r--r-- | arch/arm/mach-imx/pm-imx6.c | 25 |
1 files changed, 19 insertions, 6 deletions
diff --git a/arch/arm/mach-imx/pm-imx6.c b/arch/arm/mach-imx/pm-imx6.c index bbe449f52046..56341fba6d51 100644 --- a/arch/arm/mach-imx/pm-imx6.c +++ b/arch/arm/mach-imx/pm-imx6.c @@ -423,11 +423,10 @@ static const u32 imx6ul_mmdc_lpddr2_offset[] __initconst = { }; static const u32 imx6sll_mmdc_io_offset[] __initconst = { - 0x30c, 0x310, 0x314, 0x318, /* DQM0 ~ DQM3 */ - 0x5c4, 0x5cc, 0x5d4, 0x5d8, /* GPR_B0DS ~ GPR_B3DS */ - 0x300, 0x31c, 0x338, 0x5ac, /* CAS, RAS, SDCLK_0, GPR_ADDS */ - 0x33c, 0x340, 0x5b0, 0x5c0, /* SODT0, SODT1, MODE_CTL, MODE */ - 0x330, 0x334, 0x320, /* SDCKE0, SDCKE1, RESET */ + 0x294, 0x298, 0x29c, 0x2a0, /* DQM0 ~ DQM3 */ + 0x544, 0x54c, 0x554, 0x558, /* GPR_B0DS ~ GPR_B3DS */ + 0x530, 0x540, 0x2ac, 0x52c, /* MODE_CTL, MODE, SDCLK_0, GPR_ADDDS */ + 0x2a4, 0x2a8, /* SDCKE0, SDCKE1*/ }; static const u32 imx6sll_mmdc_lpddr3_offset[] __initconst = { @@ -598,7 +597,7 @@ struct imx6_cpu_pm_info { struct imx6_pm_base anatop_base; u32 ttbr1; /* Store TTBR1 */ u32 mmdc_io_num; /* Number of MMDC IOs which need saved/restored. */ - u32 mmdc_io_val[MX6_MAX_MMDC_IO_NUM][2]; /* To save offset and value */ + u32 mmdc_io_val[MX6_MAX_MMDC_IO_NUM][3]; /* To save offset, value, low power settings */ u32 mmdc_num; /* Number of MMDC registers which need saved/restored. */ u32 mmdc_val[MX6_MAX_MMDC_NUM][2]; } __aligned(8); @@ -1122,6 +1121,20 @@ static int __init imx6q_suspend_init(const struct imx6_pm_socdata *socdata) pm_info->mmdc_io_val[i][1] = readl_relaxed(pm_info->iomuxc_base.vbase + mmdc_io_offset_array[i]); + pm_info->mmdc_io_val[i][2] = 0; + } + + /* i.MX6SLL has no DRAM RESET pin */ + if (cpu_is_imx6sll()) { + pm_info->mmdc_io_val[pm_info->mmdc_io_num - 2][2] = 0x1000; + pm_info->mmdc_io_val[pm_info->mmdc_io_num - 1][2] = 0x1000; + } else { + if (pm_info->ddr_type == IMX_DDR_TYPE_LPDDR2) { + /* for LPDDR2, CKE0/1 and RESET pin need special setting */ + pm_info->mmdc_io_val[pm_info->mmdc_io_num - 3][2] = 0x1000; + pm_info->mmdc_io_val[pm_info->mmdc_io_num - 2][2] = 0x1000; + pm_info->mmdc_io_val[pm_info->mmdc_io_num - 1][2] = 0x80000; + } } /* initialize MMDC settings */ |