diff options
author | Arnd Bergmann <arnd@arndb.de> | 2012-01-07 11:51:28 +0000 |
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committer | Arnd Bergmann <arnd@arndb.de> | 2012-01-07 11:51:28 +0000 |
commit | 40ba95fdf158713377d47736b1b3a9d75f4f2515 (patch) | |
tree | 17a3216542d1107f777fd82577c91aebbce597d6 /arch/arm/mach-imx/src.c | |
parent | 70d84a6431d732cbc4e68e72b6890cdd3865d43d (diff) | |
parent | 0575fb754dbfc32a01f297e778533340a533ec68 (diff) |
Merge branch 'depends/rmk/restart' into next/cleanup
Conflicts:
arch/arm/mach-at91/at91cap9.c
arch/arm/mach-at91/at91sam9260.c
arch/arm/mach-at91/at91sam9261.c
arch/arm/mach-at91/at91sam9263.c
arch/arm/mach-at91/at91sam9g45.c
arch/arm/mach-at91/at91sam9rl.c
arch/arm/mach-exynos/cpu.c
arch/arm/mach-shmobile/board-kota2.c
This resolves a bunch of conflicts between the arm-soc tree
and changes from the arm tree that have gone upstream.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/mach-imx/src.c')
-rw-r--r-- | arch/arm/mach-imx/src.c | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/src.c b/arch/arm/mach-imx/src.c index a8e33681b732..4bde04f99e38 100644 --- a/arch/arm/mach-imx/src.c +++ b/arch/arm/mach-imx/src.c @@ -19,6 +19,7 @@ #define SRC_SCR 0x000 #define SRC_GPR1 0x020 +#define BP_SRC_SCR_WARM_RESET_ENABLE 0 #define BP_SRC_SCR_CORE1_RST 14 #define BP_SRC_SCR_CORE1_ENABLE 22 @@ -46,11 +47,33 @@ void imx_set_cpu_jump(int cpu, void *jump_addr) src_base + SRC_GPR1 + cpu * 8); } +void imx_src_prepare_restart(void) +{ + u32 val; + + /* clear enable bits of secondary cores */ + val = readl_relaxed(src_base + SRC_SCR); + val &= ~(0x7 << BP_SRC_SCR_CORE1_ENABLE); + writel_relaxed(val, src_base + SRC_SCR); + + /* clear persistent entry register of primary core */ + writel_relaxed(0, src_base + SRC_GPR1); +} + void __init imx_src_init(void) { struct device_node *np; + u32 val; np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-src"); src_base = of_iomap(np, 0); WARN_ON(!src_base); + + /* + * force warm reset sources to generate cold reset + * for a more reliable restart + */ + val = readl_relaxed(src_base + SRC_SCR); + val &= ~(1 << BP_SRC_SCR_WARM_RESET_ENABLE); + writel_relaxed(val, src_base + SRC_SCR); } |