diff options
| author | Anson Huang <b20788@freescale.com> | 2015-08-20 01:11:42 +0800 |
|---|---|---|
| committer | Leonard Crestez <leonard.crestez@nxp.com> | 2018-08-24 12:20:42 +0300 |
| commit | 745c477cb9c82c483380915a7505be4bb339b7c5 (patch) | |
| tree | 5f92fdab4eaef525ccd5ac3b0b02c7ffc1d54889 /arch/arm/mach-imx/suspend-imx7.S | |
| parent | 87a600cf1935a3eef1fdbc944f1c69695d175e46 (diff) | |
MLK-11391 ARM: imx: make sure SNVS clk is enabled during suspend
As SNVS clk may be disabled in kernel to save power(~1mA),
but during suspend/resume, we have to access SNVS register
to do MMDC retention and power down SoC etc.., need to
make sure SNVS clk is enabled before accessing its register.
Signed-off-by: Anson Huang <b20788@freescale.com>
Diffstat (limited to 'arch/arm/mach-imx/suspend-imx7.S')
| -rw-r--r-- | arch/arm/mach-imx/suspend-imx7.S | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/suspend-imx7.S b/arch/arm/mach-imx/suspend-imx7.S index 566a49e0313a..34910ad7c24d 100644 --- a/arch/arm/mach-imx/suspend-imx7.S +++ b/arch/arm/mach-imx/suspend-imx7.S @@ -88,6 +88,8 @@ #define DDRC_SWSTAT 0x324 #define DDRPHY_LP_CON0 0x18 +#define CCM_SNVS_LPCG 0x250 + .align 3 .macro disable_l1_dcache @@ -452,6 +454,12 @@ ENTRY(imx7_suspend) push {r4-r12} + /* make sure SNVS clk is enabled */ + ldr r11, [r0, #PM_INFO_MX7_CCM_V_OFFSET] + add r11, r11, #0x4000 + ldr r7, =0x3 + str r7, [r11, #CCM_SNVS_LPCG] + /* check whether it is a standby mode */ ldr r11, [r0, #PM_INFO_MX7_GPC_V_OFFSET] ldr r7, [r11, #GPC_PGC_C0] |