diff options
| author | Nitin Garg <nitin.garg@freescale.com> | 2015-03-27 14:47:51 -0500 |
|---|---|---|
| committer | Nitin Garg <nitin.garg@freescale.com> | 2015-09-17 09:22:18 -0500 |
| commit | 8b44de98abb0254bfbf2259673a97bd715e9f5d3 (patch) | |
| tree | d75c62b7e732ff0910e87f8e9a3d83f0109d666a /arch/arm/mach-imx/system.c | |
| parent | c34068d48273e24d392d9a49a38be807954420ed (diff) | |
MLK-10496: detect PL310 version for applying errata
Apply errata based on PL310 version instead of compile
time. Also set Prefetch offset to 15, since it improves
memcpy performance by 35%. Don't enable Incr double
Linefill enable since it adversely affects memcpy
performance by about 32MB/s and reads by 90MB/s. Tested
with 4K to 16MB sized src and dst aligned buffer.
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
Diffstat (limited to 'arch/arm/mach-imx/system.c')
| -rw-r--r-- | arch/arm/mach-imx/system.c | 14 |
1 files changed, 9 insertions, 5 deletions
diff --git a/arch/arm/mach-imx/system.c b/arch/arm/mach-imx/system.c index 2e3d6a8adac8..56693366f55b 100644 --- a/arch/arm/mach-imx/system.c +++ b/arch/arm/mach-imx/system.c @@ -140,7 +140,7 @@ void __init imx_init_l2cache(void) { void __iomem *l2x0_base; struct device_node *np; - unsigned int val; + unsigned int val, cache_id; np = of_find_compatible_node(NULL, NULL, "arm,pl310-cache"); if (!np) @@ -153,19 +153,23 @@ void __init imx_init_l2cache(void) } /* Configure the L2 PREFETCH and POWER registers */ + /* Set prefetch offset with any value except 23 as per errata 765569 */ val = readl_relaxed(l2x0_base + L2X0_PREFETCH_CTRL); - val |= 0x70800000; + val |= 0x7000000f; /* * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0 - * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2 + * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL/SX/DQP + * is r3p2. * But according to ARM PL310 errata: 752271 * ID: 752271: Double linefill feature can cause data corruption * Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2 * Workaround: The only workaround to this erratum is to disable the * double linefill feature. This is the default behavior. */ - if (cpu_is_imx6q()) - val &= ~(1 << 30 | 1 << 23); + cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID); + if (((cache_id & L2X0_CACHE_ID_PART_MASK) == L2X0_CACHE_ID_PART_L310) + && ((cache_id & L2X0_CACHE_ID_RTL_MASK) < L2X0_CACHE_ID_RTL_R3P2)) + val &= ~(1 << 30); writel_relaxed(val, l2x0_base + L2X0_PREFETCH_CTRL); val = L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN; writel_relaxed(val, l2x0_base + L2X0_POWER_CTRL); |