diff options
| author | Anson Huang <Anson.Huang@nxp.com> | 2016-02-24 11:57:02 +0800 |
|---|---|---|
| committer | Leonard Crestez <leonard.crestez@nxp.com> | 2018-08-24 12:41:33 +0300 |
| commit | 0425b49e8a7e76aff57adef84c17b300443f25b8 (patch) | |
| tree | 3c5657ddd3ce95b519d0b4f0fd8b76bda051e26a /arch/arm/mach-imx | |
| parent | e35d8a5e53861d9807eb7d623819857c3057442a (diff) | |
MLK-12443 ARM: imx: disable low power mode before entering LPSR mode
Before entering LPSR mode, as GPC was set to STOP/DSM mode already,
the wfi loop after LPSR mode would cause system enter STOP/DSM mode
first, then SNVS will force PMIC_ON_REQ to low, as SNVS needs IPG
clock to be on before entering SNVS/LPSR mode, so we have to disable
STOP/DSM mode to make sure IPG clock is on before SNVS actually enters
LPSR mode.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Diffstat (limited to 'arch/arm/mach-imx')
| -rw-r--r-- | arch/arm/mach-imx/suspend-imx7.S | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/suspend-imx7.S b/arch/arm/mach-imx/suspend-imx7.S index 7ae894c2e8c2..8a77ba953358 100644 --- a/arch/arm/mach-imx/suspend-imx7.S +++ b/arch/arm/mach-imx/suspend-imx7.S @@ -558,6 +558,12 @@ ENTRY(imx7_suspend) cmp r7, #0x0 beq ddr_retention_enter_out + /* disable STOP mode before entering LPSR */ + ldr r11, [r0, #PM_INFO_MX7_GPC_V_OFFSET] + ldr r7, [r11] + bic r7, #0xf + str r7, [r11] + /* shut down vddsoc to enter lpsr mode */ ldr r11, [r0, #PM_INFO_MX7_SNVS_V_OFFSET] ldr r7, [r11, #0x38] |