diff options
| author | Sandor Yu <R01008@freescale.com> | 2014-04-11 13:36:25 +0800 |
|---|---|---|
| committer | Nitin Garg <nitin.garg@freescale.com> | 2014-04-17 21:19:12 -0500 |
| commit | 855a2eb776dd0d048c9db7311afc719cc80b5391 (patch) | |
| tree | abfeb7e10a70f810720b99c434f78bacab1f72ae /arch/arm/mach-imx | |
| parent | 1f991ca3123275a7e47bee3badc7ed991ead3cb2 (diff) | |
ENGR00307014-04 ARM: imx6x: Set vadc clock source from Pll3
Set vadc clock parent to PLL3 USB OTG.
Signed-off-by: Sandor Yu <R01008@freescale.com>
Diffstat (limited to 'arch/arm/mach-imx')
| -rw-r--r-- | arch/arm/mach-imx/clk-imx6sx.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/clk-imx6sx.c b/arch/arm/mach-imx/clk-imx6sx.c index 9dc027ff0d96..6a5a8b543c23 100644 --- a/arch/arm/mach-imx/clk-imx6sx.c +++ b/arch/arm/mach-imx/clk-imx6sx.c @@ -504,6 +504,9 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) clk_set_parent(clks[IMX6SX_CLK_ESAI_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]); clk_set_rate(clks[IMX6SX_CLK_ESAI_PODF], 24576000); + /* Set parent clock for vadc */ + clk_set_parent(clks[IMX6SX_CLK_VID_SEL], clks[IMX6SX_CLK_PLL3_USB_OTG]); + /* default parent of can_sel clock is invalid, manually set it here */ clk_set_parent(clks[IMX6SX_CLK_CAN_SEL], clks[IMX6SX_CLK_PLL3_60M]); |