diff options
| author | Sascha Hauer <s.hauer@pengutronix.de> | 2012-11-12 15:39:55 +0100 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2012-11-16 16:33:20 +0100 |
| commit | a4dfccf8a8044fe2ed38b96e0546eaf8e669eb5f (patch) | |
| tree | 9d344c12f61ce2c3d1ca451c3f347aa9a2f6300f /arch/arm/mach-imx | |
| parent | 376aaac1837af8ed6c1014958396322c44306cbf (diff) | |
ARM i.MX51: setup MIPI during startup
The MIPI interface has to be initialized for proper IPU support.
The MIPI officially is not supported, but still needs initialization.
This patch adds this to the SoC startup as all it does is poking
some magic values into registers for which we do not have documentation.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Diffstat (limited to 'arch/arm/mach-imx')
| -rw-r--r-- | arch/arm/mach-imx/mm-imx5.c | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/mm-imx5.c b/arch/arm/mach-imx/mm-imx5.c index f92caf1b30ba..79d71cf23a1d 100644 --- a/arch/arm/mach-imx/mm-imx5.c +++ b/arch/arm/mach-imx/mm-imx5.c @@ -81,8 +81,28 @@ void __init imx50_init_early(void) mxc_arch_reset_init(MX50_IO_ADDRESS(MX50_WDOG_BASE_ADDR)); } +/* + * The MIPI HSC unit has been removed from the i.MX51 Reference Manual by + * the Freescale marketing division. However this did not remove the + * hardware from the chip which still needs to be configured for proper + * IPU support. + */ +static void __init imx51_ipu_mipi_setup(void) +{ + void __iomem *hsc_addr; + hsc_addr = MX51_IO_ADDRESS(MX51_MIPI_HSC_BASE_ADDR); + + /* setup MIPI module to legacy mode */ + __raw_writel(0xf00, hsc_addr); + + /* CSI mode: reserved; DI control mode: legacy (from Freescale BSP) */ + __raw_writel(__raw_readl(hsc_addr + 0x800) | 0x30ff, + hsc_addr + 0x800); +} + void __init imx51_init_early(void) { + imx51_ipu_mipi_setup(); mxc_set_cpu_type(MXC_CPU_MX51); mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR)); mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR)); |