diff options
| author | Fancy Fang <chen.fang@nxp.com> | 2016-04-15 18:11:51 +0800 |
|---|---|---|
| committer | Frank Li <Frank.Li@nxp.com> | 2016-05-23 15:04:05 -0500 |
| commit | 9e04de3451adc465dc239d91778cb79c95ef9f99 (patch) | |
| tree | a82854068091adc08bcface34e5829cd0c8d7883 /arch/arm/mach-imx | |
| parent | 2b25e7d3af630951d0cfe3dbe6e81e75db2a3571 (diff) | |
MLK-12699-1 ARM: imx7d: clk: add two clocks definition for pxp
The pxp require two clocks to enable when it works, and
they are 'ipg' and 'axi' clocks. Besides, the two clocks
share the same CCGR to control clock gating.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Diffstat (limited to 'arch/arm/mach-imx')
| -rw-r--r-- | arch/arm/mach-imx/clk-imx7d.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/clk-imx7d.c b/arch/arm/mach-imx/clk-imx7d.c index 980a30a92b33..c3e39eb8eb3b 100644 --- a/arch/arm/mach-imx/clk-imx7d.c +++ b/arch/arm/mach-imx/clk-imx7d.c @@ -376,6 +376,8 @@ static u32 share_count_sai1; static u32 share_count_sai2; static u32 share_count_sai3; +static u32 share_count_pxp; + static struct clk_div_table test_div_table[] = { { .val = 3, .div = 1, }, { .val = 2, .div = 1, }, @@ -862,6 +864,8 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node) clks[IMX7D_USB_PHY1_CLK] = imx_clk_gate4("usb_phy1_clk", "pll_usb1_main_clk", base + 0x46a0, 0); clks[IMX7D_USB_PHY2_CLK] = imx_clk_gate4("usb_phy2_clk", "pll_usb_main_clk", base + 0x46b0, 0); clks[IMX7D_ADC_ROOT_CLK] = imx_clk_gate4("adc_root_clk", "ipg_root_clk", base + 0x4200, 0); + clks[IMX7D_PXP_IPG_CLK] = imx_clk_gate2_shared2("pxp_ipg_clk", "ipg_root_clk", base + 0x44c0, 0, &share_count_pxp); + clks[IMX7D_PXP_AXI_CLK] = imx_clk_gate2_shared2("pxp_axi_clk", "main_axi_root_clk", base + 0x44c0, 0, &share_count_pxp); clks[IMX7D_GPT_3M_CLK] = imx_clk_fixed_factor("gpt_3m", "osc", 1, 8); |