diff options
author | Fabio Estevam <fabio.estevam@freescale.com> | 2014-08-19 15:21:12 -0300 |
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committer | Shawn Guo <shawn.guo@freescale.com> | 2014-09-16 10:06:46 +0800 |
commit | 0783a56087e9ecfae2f01f9662ff52081c5b5e25 (patch) | |
tree | da9719b2d2478b123e13aa1cf6ac0bd5b2d7cdaf /arch/arm/mach-imx | |
parent | bad66c3ebdcdb4043bdcfe24ddab4802d5fc4327 (diff) |
ARM: clk-imx6sl: Select appropriate parents for LCDIF clocks
PLL5 is well suited for being the parent of IMX6SL_CLK_LCDIF_PIX_SEL and
PLL2_PFD for IMX6SL_CLK_LCDIF_AXI_SEL.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Diffstat (limited to 'arch/arm/mach-imx')
-rw-r--r-- | arch/arm/mach-imx/clk-imx6sl.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/clk-imx6sl.c b/arch/arm/mach-imx/clk-imx6sl.c index ba3af22c1266..11908e8bf9ab 100644 --- a/arch/arm/mach-imx/clk-imx6sl.c +++ b/arch/arm/mach-imx/clk-imx6sl.c @@ -376,6 +376,13 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node) /* Audio-related clocks configuration */ clk_set_parent(clks[IMX6SL_CLK_SPDIF0_SEL], clks[IMX6SL_CLK_PLL3_PFD3]); + /* set PLL5 video as lcdif pix parent clock */ + clk_set_parent(clks[IMX6SL_CLK_LCDIF_PIX_SEL], + clks[IMX6SL_CLK_PLL5_VIDEO_DIV]); + + clk_set_parent(clks[IMX6SL_CLK_LCDIF_AXI_SEL], + clks[IMX6SL_CLK_PLL2_PFD2]); + /* Set initial power mode */ imx6q_set_lpm(WAIT_CLOCKED); } |