diff options
| author | Huang Shijie <b32955@freescale.com> | 2014-03-18 16:51:06 +0800 |
|---|---|---|
| committer | Nitin Garg <nitin.garg@freescale.com> | 2014-04-16 08:58:12 -0500 |
| commit | 1ddd70da4ce5558d0b0a76cadae263a648628d7a (patch) | |
| tree | 589ccf9f459969c8defbfef6328f0e14e57981a3 /arch/arm/mach-imx | |
| parent | 4cc306e55c1077e119aa025737b9747fa4ce3dc8 (diff) | |
ENGR00303701-3 ARM: clk: imx6sx: use the 132MHz for the WEIM
We set the maximum clock frequency for the WEIM module.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Diffstat (limited to 'arch/arm/mach-imx')
| -rw-r--r-- | arch/arm/mach-imx/clk-imx6sx.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/clk-imx6sx.c b/arch/arm/mach-imx/clk-imx6sx.c index 9984762ee966..5b9735c7388a 100644 --- a/arch/arm/mach-imx/clk-imx6sx.c +++ b/arch/arm/mach-imx/clk-imx6sx.c @@ -451,6 +451,10 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) clk_prepare_enable(clks[IMX6SX_CLK_USBPHY2_GATE]); } + /* Set the default 132MHz for EIM module */ + clk_set_parent(clks[IMX6SX_CLK_EIM_SLOW_SEL], clks[IMX6SX_CLK_PLL2_PFD2]); + clk_set_rate(clks[IMX6SX_CLK_EIM_SLOW], 132000000); + /* set parent clock for LCDIF1 pixel clock */ clk_set_parent(clks[IMX6SX_CLK_LCDIF1_PRE_SEL], clks[IMX6SX_CLK_PLL5_VIDEO_DIV]); clk_set_parent(clks[IMX6SX_CLK_LCDIF1_SEL], clks[IMX6SX_CLK_LCDIF1_PODF]); |