Merge branch 'next/board' of git://git.linaro.org/people/arnd/arm-soc

* 'next/board' of git://git.linaro.org/people/arnd/arm-soc: (34 commits)
  ep93xx: add support Vision EP9307 SoM
  ARM: mxs: Add initial support for DENX MX28
  ARM: EXYNOS4: Add support SMDK4412 Board
  ARM: EXYNOS4: Add MCT support for EXYNOS4412
  ARM: EXYNOS4: Add functions for gic interrupt handling
  ARM: EXYNOS4: Add support clock for EXYNOS4412
  ARM: EXYNOS4: Add support new EXYNOS4412 SoC
  ARM: EXYNOS4: Add support MCT PPI for EXYNOS4212
  ARM: EXYNOS4: Add support PPI in external GIC
  ARM: EXYNOS4: convert boot_params to atag_offset
  ixp4xx: support omicron ixp425 based boards
  ARM: EXYNOS4: Add support SMDK4212 Board
  ARM: EXYNOS4: Add support PM for EXYNOS4212
  ARM: EXYNOS4: Add support clock for EXYNOS4212
  ARM: EXYNOS4: Add support new EXYNOS4212 SoC
  at91: USB-A9G20 C01 & C11 board support
  at91: merge board USB-A9260 and USB-A9263 together
  at91: add support for RSIs EWS board
  ARM: SAMSUNG: Fix mask value for S5P64X0 CPU IDs
  ARM: SAMSUNG: Fix mask for S3C64xx CPU IDs
  ...

1 files changed, 78 insertions, 0 deletions

diff --git a/arch/arm/mach-ixp4xx/miccpt-pci.c b/arch/arm/mach-ixp4xx/miccpt-pci.c
new file mode 100644
index 000000000000..ca0bae7fca90
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/miccpt-pci.c
@@ -0,0 +1,78 @@
+/*
+ * arch/arm/mach-ixp4xx/miccpt-pci.c
+ *
+ * MICCPT board-level PCI initialization
+ *
+ * Copyright (C) 2002 Intel Corporation.
+ * Copyright (C) 2003-2004 MontaVista Software, Inc.
+ * Copyright (C) 2006 OMICRON electronics GmbH
+ *
+ * Author: Michael Jochum <michael.jochum@omicron.at>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/irq.h>
+#include <asm/mach/pci.h>
+#include <asm/irq.h>
+#include <mach/hardware.h>
+#include <asm/mach-types.h>
+
+#define MAX_DEV		4
+#define IRQ_LINES	4
+
+/* PCI controller GPIO to IRQ pin mappings */
+#define INTA		1
+#define INTB		2
+#define INTC		3
+#define INTD		4
+
+
+void __init miccpt_pci_preinit(void)
+{
+	irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
+	irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
+	irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
+	irq_set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW);
+	ixp4xx_pci_preinit();
+}
+
+static int __init miccpt_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+{
+	static int pci_irq_table[IRQ_LINES] = {
+		IXP4XX_GPIO_IRQ(INTA),
+		IXP4XX_GPIO_IRQ(INTB),
+		IXP4XX_GPIO_IRQ(INTC),
+		IXP4XX_GPIO_IRQ(INTD)
+	};
+
+	if (slot >= 1 && slot <= MAX_DEV && pin >= 1 && pin <= IRQ_LINES)
+		return pci_irq_table[(slot + pin - 2) % 4];
+
+	return -1;
+}
+
+struct hw_pci miccpt_pci __initdata = {
+	.nr_controllers = 1,
+	.preinit	= miccpt_pci_preinit,
+	.swizzle	= pci_std_swizzle,
+	.setup		= ixp4xx_setup,
+	.scan		= ixp4xx_scan_bus,
+	.map_irq	= miccpt_map_irq,
+};
+
+int __init miccpt_pci_init(void)
+{
+	if (machine_is_miccpt())
+		pci_common_init(&miccpt_pci);
+	return 0;
+}
+
+subsys_initcall(miccpt_pci_init);