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authorThomas Petazzoni <thomas.petazzoni@free-electrons.com>2012-09-11 14:27:15 +0200
committerJason Cooper <jason@lakedaemon.net>2012-09-21 18:02:54 +0000
commit40306c8bc0dbef623fa02815929dace1c75046e2 (patch)
tree5ad02deee6a0c0900ee4801173300d7c3c03824b /arch/arm/mach-kirkwood/include/mach/bridge-regs.h
parent73b39d4b443857c2155c7269bb593748f48d4852 (diff)
arm: mach-kirkwood: use plus instead of or for address definitions
Since we are going to use IOMEM() to define many base virtual addresses, we can no longer use binary or to define the individual register addresses ("binary or" arithmetic on pointers is not allowed). Instead, use the more conventional plus operator to do so. The binary or operators were actually not useful because the low-order bits of the base address were always zero, so the usage of the binary or operators was effectively identical to a plus operator. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Tested-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Diffstat (limited to 'arch/arm/mach-kirkwood/include/mach/bridge-regs.h')
-rw-r--r--arch/arm/mach-kirkwood/include/mach/bridge-regs.h20
1 files changed, 10 insertions, 10 deletions
diff --git a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
index a115142f8690..5c82b7dce4e2 100644
--- a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
+++ b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
@@ -13,37 +13,37 @@
#include <mach/kirkwood.h>
-#define CPU_CONFIG (BRIDGE_VIRT_BASE | 0x0100)
+#define CPU_CONFIG (BRIDGE_VIRT_BASE + 0x0100)
#define CPU_CONFIG_ERROR_PROP 0x00000004
-#define CPU_CONTROL (BRIDGE_VIRT_BASE | 0x0104)
+#define CPU_CONTROL (BRIDGE_VIRT_BASE + 0x0104)
#define CPU_RESET 0x00000002
-#define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108)
+#define RSTOUTn_MASK (BRIDGE_VIRT_BASE + 0x0108)
#define WDT_RESET_OUT_EN 0x00000002
#define SOFT_RESET_OUT_EN 0x00000004
-#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c)
+#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE + 0x010c)
#define SOFT_RESET 0x00000001
-#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE | 0x0110)
+#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE + 0x0110)
#define WDT_INT_REQ 0x0008
#define BRIDGE_INT_TIMER1_CLR (~0x0004)
-#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200)
+#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0200)
#define IRQ_CAUSE_LOW_OFF 0x0000
#define IRQ_MASK_LOW_OFF 0x0004
#define IRQ_CAUSE_HIGH_OFF 0x0010
#define IRQ_MASK_HIGH_OFF 0x0014
-#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300)
-#define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE | 0x0300)
+#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0300)
+#define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE + 0x0300)
-#define L2_CONFIG_REG (BRIDGE_VIRT_BASE | 0x0128)
+#define L2_CONFIG_REG (BRIDGE_VIRT_BASE + 0x0128)
#define L2_WRITETHROUGH 0x00000010
-#define CLOCK_GATING_CTRL (BRIDGE_VIRT_BASE | 0x11c)
+#define CLOCK_GATING_CTRL (BRIDGE_VIRT_BASE + 0x11c)
#define CGC_BIT_GE0 (0)
#define CGC_BIT_PEX0 (2)
#define CGC_BIT_USB0 (3)