diff options
| author | Andrew Lunn <andrew@lunn.ch> | 2011-12-15 08:15:07 +0100 |
|---|---|---|
| committer | Mike Turquette <mturquette@linaro.org> | 2012-05-08 16:33:39 -0700 |
| commit | 2f129bf4aab684bef1e82e747b709a5025ecb698 (patch) | |
| tree | 4be6e04fc306cfad25b3b86f831cd4d462c10f44 /arch/arm/mach-mv78xx0 | |
| parent | f0948f59dbc8e725a96ba16da666e8f5cdd43ba8 (diff) | |
ARM: Orion: Add clocks using the generic clk infrastructure.
Add tclk as a fixed rate clock for all platforms. In addition, on
kirkwood, add a gated clock for most of the clocks which can be gated.
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Jamie Lentin <jm@lentin.co.uk>
[mturquette@linaro.org: removed redundant CLKDEV_LOOKUP from Kconfig]
[mturquette@linaro.org: removed redundant clk.h from mach-dove/common.c]
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Diffstat (limited to 'arch/arm/mach-mv78xx0')
| -rw-r--r-- | arch/arm/mach-mv78xx0/common.c | 27 |
1 files changed, 20 insertions, 7 deletions
diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c index a5dcf766a3f9..73733207f5a9 100644 --- a/arch/arm/mach-mv78xx0/common.c +++ b/arch/arm/mach-mv78xx0/common.c @@ -13,6 +13,7 @@ #include <linux/platform_device.h> #include <linux/serial_8250.h> #include <linux/ata_platform.h> +#include <linux/clk-provider.h> #include <linux/ethtool.h> #include <asm/mach/map.h> #include <asm/mach/time.h> @@ -103,24 +104,24 @@ static void get_pclk_l2clk(int hclk, int core_index, int *pclk, int *l2clk) static int get_tclk(void) { - int tclk; + int tclk_freq; /* * TCLK tick rate is configured by DEV_A[2:0] strap pins. */ switch ((readl(SAMPLE_AT_RESET_HIGH) >> 6) & 7) { case 1: - tclk = 166666667; + tclk_freq = 166666667; break; case 3: - tclk = 200000000; + tclk_freq = 200000000; break; default: panic("unknown TCLK PLL setting: %.8x\n", readl(SAMPLE_AT_RESET_HIGH)); } - return tclk; + return tclk_freq; } @@ -166,6 +167,17 @@ void __init mv78xx0_map_io(void) /***************************************************************************** + * CLK tree + ****************************************************************************/ +static struct clk *tclk; + +static void __init clk_init(void) +{ + tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT, + get_tclk()); +} + +/***************************************************************************** * EHCI ****************************************************************************/ void __init mv78xx0_ehci0_init(void) @@ -378,25 +390,26 @@ void __init mv78xx0_init(void) int hclk; int pclk; int l2clk; - int tclk; core_index = mv78xx0_core_index(); hclk = get_hclk(); get_pclk_l2clk(hclk, core_index, &pclk, &l2clk); - tclk = get_tclk(); printk(KERN_INFO "%s ", mv78xx0_id()); printk("core #%d, ", core_index); printk("PCLK = %dMHz, ", (pclk + 499999) / 1000000); printk("L2 = %dMHz, ", (l2clk + 499999) / 1000000); printk("HCLK = %dMHz, ", (hclk + 499999) / 1000000); - printk("TCLK = %dMHz\n", (tclk + 499999) / 1000000); + printk("TCLK = %dMHz\n", (get_tclk() + 499999) / 1000000); mv78xx0_setup_cpu_mbus(); #ifdef CONFIG_CACHE_FEROCEON_L2 feroceon_l2_init(is_l2_writethrough()); #endif + + /* Setup root of clk tree */ + clk_init(); } void mv78xx0_restart(char mode, const char *cmd) |