diff options
author | Russell Robinson Jr <rrobinson@phytec.com> | 2013-03-14 13:25:05 -0700 |
---|---|---|
committer | Russell Robinson Jr <rrobinson@phytec.com> | 2013-03-14 17:31:28 -0700 |
commit | 89df1897f9e305288503bccac1b7de0c196dca48 (patch) | |
tree | 0a3e237bd5bd9061767b70691e856623e92c7071 /arch/arm/mach-mvf | |
parent | 16af5ee7d9556c47b332788e4107cbed5ee7ec10 (diff) |
pcm052: audio: audio playback and record support added
Signed-off-by: Russell Robinson Jr <rrobinson@phytec.com>
Diffstat (limited to 'arch/arm/mach-mvf')
-rw-r--r-- | arch/arm/mach-mvf/board-pcm052.c | 32 | ||||
-rw-r--r-- | arch/arm/mach-mvf/clock.c | 34 | ||||
-rw-r--r-- | arch/arm/mach-mvf/crm_regs.h | 16 |
3 files changed, 55 insertions, 27 deletions
diff --git a/arch/arm/mach-mvf/board-pcm052.c b/arch/arm/mach-mvf/board-pcm052.c index 84bd65623ebb..8048349afae7 100644 --- a/arch/arm/mach-mvf/board-pcm052.c +++ b/arch/arm/mach-mvf/board-pcm052.c @@ -147,14 +147,14 @@ static iomux_v3_cfg_t pcm052_pads[] = { #endif /*SAI2*/ -// MVF600_PAD6_PTA16_SAI2_TX_BCLK, + MVF600_PAD6_PTA16_SAI2_TX_BCLK, MVF600_PAD8_PTA18_SAI2_TX_DATA, -// MVF600_PAD3_PTA10_SAI2_TX_SYNC, // originally PAD9_PTA19 - MVF600_PAD11_PTA21_SAI2_RX_BCLK, -// MVF600_PAD23_PTB1_SAI2_RX_DATA, // originally PAD12_PTA22 -// MVF600_PAD13_PTA23_SAI2_RX_SYNC, // UNUSED + MVF600_PAD9_PTA19_SAI2_TX_SYNC, +// MVF600_PAD11_PTA21_SAI2_RX_BCLK, + MVF600_PAD23_PTB1_SAI2_RX_DATA, // originally PAD12_PTA22 +// MVF600_PAD24_PTB2_SAI2_RX_SYNC, // originally PAD13_PTA23 // MVF600_PAD40_PTB18_EXT_AUDIO_MCLK, // UNUSED -// MVF600_PAD33_PTB11__CKO2, // phyCORE MCLK + MVF600_PAD33_PTB11__CKO2, // phyCORE MCLK /*DCU0*/ MVF600_PAD25_PTB3_LCD_ENABLE, @@ -204,15 +204,15 @@ static iomux_v3_cfg_t pcm052_pads[] = { * FTM0 CH0~3 are connected to demo LED0~3 * PAD30 mux with LCD enable signal */ - MVF600_PAD22_PTB0_FTM0CH0, - MVF600_PAD23_PTB1_FTM0CH1, - MVF600_PAD24_PTB2_FTM0CH2, +// MVF600_PAD22_PTB0_FTM0CH0, +// MVF600_PAD23_PTB1_FTM0CH1, +// MVF600_PAD24_PTB2_FTM0CH2, // MVF600_PAD25_PTB3_FTM0CH3, - MVF600_PAD28_PTB6_FTM0CH6, - MVF600_PAD29_PTB7_FTM0CH7, +// MVF600_PAD28_PTB6_FTM0CH6, +// MVF600_PAD29_PTB7_FTM0CH7, /*MVF600_PAD30_PTB8_FTM1CH0,*/ - MVF600_PAD31_PTB9_FTM1CH1, +// MVF600_PAD31_PTB9_FTM1CH1, /* Touch Screen */ MVF600_PAD32_PTB10_TS_IRQ, @@ -236,7 +236,7 @@ static struct mxc_audio_platform_data pcm052_audio_data; static int pcm052_sgtl5000_init(void) { - pcm052_audio_data.sysclk = 24576000; + pcm052_audio_data.sysclk = 12288000; return 0; } @@ -252,7 +252,7 @@ static struct mxc_audio_platform_data pcm052_audio_data = { }; static struct platform_device pcm052_audio_device = { - .name = "mvf-sgtl5000", + .name = "pcm052-sgtl5000", }; static struct imxuart_platform_data mvf_uart1_pdata = { @@ -523,8 +523,8 @@ static void __init pcm052_board_init(void) mvfa5_add_dcu(0, &mvf_dcu_pdata); -// mxc_register_device(&pcm052_audio_device, &pcm052_audio_data); -// mvfa5_add_sai(2, &mvf_sai_pdata); + mxc_register_device(&pcm052_audio_device, &pcm052_audio_data); + mvfa5_add_sai(2, &mvf_sai_pdata); // mvf_add_wdt(0); diff --git a/arch/arm/mach-mvf/clock.c b/arch/arm/mach-mvf/clock.c index 74ce8a9f290e..199483ccb32a 100644 --- a/arch/arm/mach-mvf/clock.c +++ b/arch/arm/mach-mvf/clock.c @@ -1389,7 +1389,7 @@ static struct clk dcu0_clk = { static unsigned long get_audio_external_clock_rate(struct clk *clk) { - return 24576000; + return 24567000; } static struct clk audio_external_clk = { @@ -1405,11 +1405,10 @@ static int _clk_sai2_set_parent(struct clk *clk, struct clk *parent) mux = _get_mux6(parent, &audio_external_clk, NULL, NULL, &pll4_audio_main_clk, NULL, NULL); - + reg |= (mux << MXC_CCM_CSCMR1_SAI2_CLK_SEL_OFFSET); - __raw_writel(reg, MXC_CCM_CSCMR1); - + return 0; } @@ -1448,10 +1447,18 @@ static int _clk_sai2_enable(struct clk *clk) { u32 reg; + /* enable SAI2 clock */ reg = __raw_readl(MXC_CCM_CSCDR1); - reg |= MXC_CCM_CSCDR1_SAI2_EN; + reg |= MXC_CCM_CSCDR1_SAI2_EN | (0xF << MXC_CCM_CSCDR1_SAI2_DIV_OFFSET); __raw_writel(reg, MXC_CCM_CSCDR1); + /* enable CKO2 observation of SAI2 */ + reg = __raw_readl(MXC_CCM_CCOSR) + & ~MXC_CCM_CCOSR_CKO2_SEL_MASK; + reg |= MXC_CCM_CCOSR_CKO2_EN | MXC_CCM_CCOSR_CKO2_SEL_SAI2 | + (2 << MXC_CCM_CCOSR_CKO2_DIV_OFFSET); + __raw_writel(reg, MXC_CCM_CCOSR); + return 0; } @@ -1459,10 +1466,16 @@ static void _clk_sai2_disable(struct clk *clk) { u32 reg; + /* disable SAI2 clock */ reg = __raw_readl(MXC_CCM_CSCDR1); reg &= ~MXC_CCM_CSCDR1_SAI2_EN; __raw_writel(reg, MXC_CCM_CSCDR1); + /* disable CKO2 observation of SAI2 */ + reg = __raw_readl(MXC_CCM_CCOSR); + reg &= ~MXC_CCM_CCOSR_CKO2_EN; + __raw_writel(reg, MXC_CCM_CCOSR); + return 0; } @@ -1488,7 +1501,7 @@ static unsigned long _clk_sai_round_rate(struct clk *clk, static struct clk sai2_clk = { __INIT_CLK_DEBUG(sai2_clk) - .parent = &audio_external_clk, + .parent = &pll4_audio_main_clk, .enable_reg = MXC_CCM_CCGR1, .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET, .enable = _clk_sai2_enable, @@ -1926,7 +1939,7 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK(NULL, "cpu_clk", cpu_clk), /* arm core clk */ _REGISTER_CLOCK(NULL, "periph_clk", periph_clk), /* platform bus clk */ _REGISTER_CLOCK(NULL, "ipg_clk", ipg_clk), -// _REGISTER_CLOCK(NULL, "audio ext clk", audio_external_clk), + _REGISTER_CLOCK(NULL, "audio ext clk", audio_external_clk), _REGISTER_CLOCK(NULL, "mvf-uart.0", uart_clk[0]), _REGISTER_CLOCK(NULL, "mvf-uart.1", uart_clk[0]), _REGISTER_CLOCK(NULL, "mvf-uart.2", uart_clk[0]), @@ -1940,8 +1953,7 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK("imx2-wdt.0", NULL, dummy_clk), _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, esdhc1_clk), _REGISTER_CLOCK("mvf-dcu.0", NULL, dcu0_clk), -// _REGISTER_CLOCK("mvf-sai.0", NULL, sai2_clk), -// _REGISTER_CLOCK(NULL, "i2c_clk", i2c_clk[2]), + _REGISTER_CLOCK("mvf-sai.0", NULL, sai2_clk), _REGISTER_CLOCK("imx-i2c.2", NULL, i2c_clk[2]), _REGISTER_CLOCK(NULL, "usb-clk", usb_clk), _REGISTER_CLOCK(NULL, "mvf-usb.0", usb_phy0_clk), @@ -2018,8 +2030,8 @@ int __init mvf_clocks_init(unsigned long ckil, unsigned long osc, clk_set_parent(&dcu0_clk, &pll1_pfd2_452M); clk_set_rate(&dcu0_clk, 113000000); - clk_set_parent(&sai2_clk, &audio_external_clk); - clk_set_rate(&sai2_clk, 24576000); + clk_set_parent(&sai2_clk, &pll4_audio_main_clk); + clk_set_rate(&sai2_clk, 24567000); clk_set_parent(&qspi0_clk, &pll1_pfd4_528M); clk_set_rate(&qspi0_clk, 66000000); diff --git a/arch/arm/mach-mvf/crm_regs.h b/arch/arm/mach-mvf/crm_regs.h index 57fac5bbe973..4cfc7898aa87 100644 --- a/arch/arm/mach-mvf/crm_regs.h +++ b/arch/arm/mach-mvf/crm_regs.h @@ -185,6 +185,10 @@ #define MXC_CCM_BASE MVF_IO_ADDRESS(MVF_CCM_BASE_ADDR) +#define MVF_I2S0_BASE MVF_IO_ADDRESS(MVF_I2S0_BASE_ADDR) +#define MVF_I2S0_TCR2 (MVF_I2S0_BASE + 0xF008) +#define MVF_I2S0_RCR2 (MVF_I2S0_BASE + 0xF088) + /* Register addresses of CCM*/ #define MXC_CCM_CCR (MXC_CCM_BASE + 0x00) #define MXC_CCM_CSR (MXC_CCM_BASE + 0x04) @@ -199,6 +203,7 @@ #define MXC_CCM_CLPCR (MXC_CCM_BASE + 0x2c) #define MXC_CCM_CISR (MXC_CCM_BASE + 0x30) #define MXC_CCM_CIMR (MXC_CCM_BASE + 0x34) +#define MXC_CCM_CCOSR (MXC_CCM_BASE + 0x38) #define MXC_CCM_CGPR (MXC_CCM_BASE + 0x3c) #define MXC_CCM_CCGR0 (MXC_CCM_BASE + 0x40) #define MXC_CCM_CCGR1 (MXC_CCM_BASE + 0x44) @@ -435,6 +440,17 @@ #define MXC_CCM_CIMR_LRF_PLL2 (1 << 1) #define MXC_CCM_CIMR_LRF_PLL1 (1) +/* CCOSR */ +#define MXC_CCM_CCOSR_CKO2_EN (1 << 26) +#define MXC_CCM_CCOSR_CKO2_DIV_OFFSET (22) + +#define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x3F << 16) +#define MXC_CCM_CCOSR_CKO2_SEL_SAI2 (0xD << 16) +#define MXC_CCM_CCOSR_CKO2_SEL_PLL4_MAIN (0x1A << 16) + +#define MXC_CCM_CCOSR_CKO1_EN (1 << 10) +#define MXC_CCM_CCOSR_CKO1_DIV_OFFSET (6) + /* Define the bits in registers CGPR */ #define MXC_CCM_CGPR_EFUSE_PROG (1 << 4) #define MXC_CCM_CGPR_QSPI1_ACCZ (1 << 1) |