diff options
| author | Richard Zhu <r65037@freescale.com> | 2010-02-25 17:58:05 +0800 |
|---|---|---|
| committer | Alejandro Gonzalez <alex.gonzalez@digi.com> | 2010-05-25 11:17:15 +0200 |
| commit | 4d658511fd473c68173b27ea016a7003f0ff2312 (patch) | |
| tree | ff846cb8ee7d9a5ce502251a864e58af2542b50e /arch/arm/mach-mx28 | |
| parent | 90c2e94fe8b2bf3e311e9f50de09b6d87580c1f6 (diff) | |
ENGR00120678 [MX28] Can not detect SD/MMC card after uboot from nfs
The incorrect ssp parent clock configuration causes the issue.
Signed-off-by: Richard Zhu <r65037@freescale.com>
Signed-off-by: Alejandro Gonzalez <alex.gonzalez@digi.com>
Diffstat (limited to 'arch/arm/mach-mx28')
| -rw-r--r-- | arch/arm/mach-mx28/clock.c | 26 |
1 files changed, 22 insertions, 4 deletions
diff --git a/arch/arm/mach-mx28/clock.c b/arch/arm/mach-mx28/clock.c index 2ee74b359ad0..fd4695e4a7d4 100644 --- a/arch/arm/mach-mx28/clock.c +++ b/arch/arm/mach-mx28/clock.c @@ -883,12 +883,14 @@ static int ssp_set_parent(struct clk *clk, struct clk *parent) if (clk->bypass_reg) { if (clk->parent == parent) + return 0; + if (parent == &ref_io_clk[0] || parent == &ref_io_clk[1]) __raw_writel(1 << clk->bypass_bits, - clk->bypass_reg + SET_REGISTER); - else - __raw_writel(0 << clk->bypass_bits, clk->bypass_reg + CLR_REGISTER); - + else + __raw_writel(1 << clk->bypass_bits, + clk->bypass_reg + SET_REGISTER); + clk->parent = parent; ret = 0; } @@ -935,6 +937,14 @@ static struct clk ssp_clk[] = { .disable = mx28_raw_disable, .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP2, .enable_bits = BM_CLKCTRL_SSP2_CLKGATE, + .busy_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP2, + .busy_bits = 29, + .scale_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP2, + .scale_bits = 0, + .bypass_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ, + .bypass_bits = 5, + .set_rate = ssp_set_rate, + .set_parent = ssp_set_parent, }, { .parent = &ref_io_clk[1], @@ -943,6 +953,14 @@ static struct clk ssp_clk[] = { .disable = mx28_raw_disable, .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP3, .enable_bits = BM_CLKCTRL_SSP3_CLKGATE, + .busy_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP3, + .busy_bits = 29, + .scale_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP3, + .scale_bits = 0, + .bypass_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ, + .bypass_bits = 6, + .set_rate = ssp_set_rate, + .set_parent = ssp_set_parent, }, }; |