diff options
| author | Ranjani Vaidyanathan-RA5478 <Ranjani.Vaidyanathan@freescale.com> | 2010-04-22 15:06:01 -0500 |
|---|---|---|
| committer | Alejandro Gonzalez <alex.gonzalez@digi.com> | 2010-05-25 11:20:26 +0200 |
| commit | 75bdcb0526e4759cdd120f888b0b8ad2c227845e (patch) | |
| tree | 28b96d22d03c93561e72e6dc0549094912a804ea /arch/arm/mach-mx5/bus_freq.c | |
| parent | 8bd9d840ccccbd24ff3f40105f1d8b323dd0cfc4 (diff) | |
ENGR00122789: Fixed long-term video playback issue.
Fixed long-term video playback issue due to incorrect increment of
clock usecount.
Fixed various bugs associated with system entering LP-APM mode.
Fixed incorrect enabling of PLL3 that was not allowing system to enter
LP-APM mode if TVE was built in.
EMI_GARB clock needs to be enabled when certain clock dividers are changed.
Signed-off-by: Ranjani Vaidyanathan-RA5478 <Ranjani.Vaidyanathan@freescale.com>
Signed-off-by: Alejandro Gonzalez <alex.gonzalez@digi.com>
Diffstat (limited to 'arch/arm/mach-mx5/bus_freq.c')
| -rw-r--r-- | arch/arm/mach-mx5/bus_freq.c | 20 |
1 files changed, 15 insertions, 5 deletions
diff --git a/arch/arm/mach-mx5/bus_freq.c b/arch/arm/mach-mx5/bus_freq.c index 1463ef4df254..cf957ea7ba54 100644 --- a/arch/arm/mach-mx5/bus_freq.c +++ b/arch/arm/mach-mx5/bus_freq.c @@ -65,7 +65,8 @@ static struct clk *periph_apm_clk; static struct clk *lp_apm; static struct clk *osc; static struct clk *gpc_dvfs_clk; -static struct clk *mipi_hsp_clk; +static struct clk *emi_garb_clk; + struct regulator *lp_regulator; int low_bus_freq_mode; int high_bus_freq_mode; @@ -135,8 +136,11 @@ int set_low_bus_freq(void) | 3 << MXC_CCM_CBCDR_NFC_PODF_OFFSET); __raw_writel(reg, MXC_CCM_CBCDR); + clk_enable(emi_garb_clk); while (__raw_readl(MXC_CCM_CDHIPR) & 0x1F) udelay(10); + clk_disable(emi_garb_clk); + /* Set the source of Periph_APM_Clock to be lp-apm. */ clk_set_parent(periph_apm_clk, lp_apm); @@ -176,8 +180,11 @@ int set_high_bus_freq(int high_bus_freq) | 4 << MXC_CCM_CBCDR_EMI_PODF_OFFSET | 3 << MXC_CCM_CBCDR_NFC_PODF_OFFSET); __raw_writel(reg, MXC_CCM_CBCDR); + + clk_enable(emi_garb_clk); while (__raw_readl(MXC_CCM_CDHIPR) & 0x1F) udelay(10); + clk_disable(emi_garb_clk); low_bus_freq_mode = 0; high_bus_freq_mode = 1; @@ -402,11 +409,14 @@ static int __devinit busfreq_probe(struct platform_device *pdev) return PTR_ERR(ipu_clk); } - mipi_hsp_clk = clk_get(NULL, "mipi_hsp_clk"); - if (IS_ERR(mipi_hsp_clk)) { - printk(KERN_DEBUG "%s: failed to get mipi_hsp_clk\n", + if (cpu_is_mx51()) + emi_garb_clk = clk_get(NULL, "emi_garb_clk"); + else + emi_garb_clk = clk_get(NULL, "emi_intr_clk.1"); + if (IS_ERR(emi_garb_clk)) { + printk(KERN_DEBUG "%s: failed to get emi_garb_clk\n", __func__); - return PTR_ERR(mipi_hsp_clk); + return PTR_ERR(emi_garb_clk); } vpu_clk = clk_get(NULL, "vpu_clk"); |