Linux 2.6.31 Release for Digi ConnectCore Wi-i.MX boards2.6.31-digi-201102101717

1 files changed, 192 insertions, 29 deletions

diff --git a/arch/arm/mach-mx5/crm_regs.h b/arch/arm/mach-mx5/crm_regs.h
index e53f55d258eb..b2660a34c0e9 100644
--- a/arch/arm/mach-mx5/crm_regs.h
+++ b/arch/arm/mach-mx5/crm_regs.h
@@ -13,17 +13,7 @@
 #ifndef __ARCH_ARM_MACH_MX51_CRM_REGS_H__
 #define __ARCH_ARM_MACH_MX51_CRM_REGS_H__
 
-extern void __iomem *ccm_base;
-extern void __iomem *pll1_base;
-extern void __iomem *pll2_base;
-extern void __iomem *pll3_base;
-extern void __iomem *pll4_base;
-
 #define MXC_CCM_BASE	(IO_ADDRESS(CCM_BASE_ADDR))
-#define MXC_DPLL1_BASE	(pll1_base)
-#define MXC_DPLL2_BASE	(pll2_base)
-#define MXC_DPLL3_BASE	(pll3_base)
-#define MXC_DPLL4_BASE (pll4_base)
 
 /* PLL Register Offsets */
 #define MXC_PLL_DP_CTL			0x00
@@ -80,6 +70,56 @@ extern void __iomem *pll4_base;
 #define MXC_PLL_DP_DESTAT_TOG_SEL	(1 << 31)
 #define MXC_PLL_DP_DESTAT_MFN		0x07FFFFFF
 
+/* Register addresses of apll and pfd*/
+#define MXC_ANADIG_FRAC0		0x10
+#define MXC_ANADIG_FRAC0_SET		0x14
+#define MXC_ANADIG_FRAC0_CLR		0x18
+#define MXC_ANADIG_FRAC1		0x20
+#define MXC_ANADIG_FRAC1_SET		0x24
+#define MXC_ANADIG_FRAC1_CLR		0x28
+#define MXC_ANADIG_MISC			0x60
+#define MXC_ANADIG_MISC_SET		0x64
+#define MXC_ANADIG_MISC_CLR		0x68
+#define MXC_ANADIG_PLLCTRL		0x70
+#define MXC_ANADIG_PLLCTRL_SET		0x74
+#define MXC_ANADIG_PLLCTRL_CLR		0x78
+
+/* apll and pfd Register Bit definitions */
+
+#define MXC_ANADIG_PFD3_CLKGATE		(1 << 31)
+#define MXC_ANADIG_PFD3_STABLE		(1 << 30)
+#define MXC_ANADIG_PFD3_FRAC_OFFSET	24
+#define MXC_ANADIG_PFD_FRAC_MASK	0x3F
+#define MXC_ANADIG_PFD2_CLKGATE		(1 << 23)
+#define MXC_ANADIG_PFD2_STABLE		(1 << 22)
+#define MXC_ANADIG_PFD2_FRAC_OFFSET	16
+#define MXC_ANADIG_PFD1_CLKGATE		(1 << 15)
+#define MXC_ANADIG_PFD1_STABLE		(1 << 14)
+#define MXC_ANADIG_PFD1_FRAC_OFFSET	8
+#define MXC_ANADIG_PFD0_CLKGATE		(1 << 7)
+#define MXC_ANADIG_PFD0_STABLE		(1 << 6)
+#define MXC_ANADIG_PFD0_FRAC_OFFSET	0
+
+#define MXC_ANADIG_PFD7_CLKGATE		(1 << 31)
+#define MXC_ANADIG_PFD7_STABLE		(1 << 30)
+#define MXC_ANADIG_PFD7_FRAC_OFFSET	24
+#define MXC_ANADIG_PFD6_CLKGATE		(1 << 23)
+#define MXC_ANADIG_PFD6_STABLE		(1 << 22)
+#define MXC_ANADIG_PFD6_FRAC_OFFSET	16
+#define MXC_ANADIG_PFD5_CLKGATE		(1 << 15)
+#define MXC_ANADIG_PFD5_STABLE		(1 << 14)
+#define MXC_ANADIG_PFD5_FRAC_OFFSET	8
+#define MXC_ANADIG_PFD4_CLKGATE		(1 << 7)
+#define MXC_ANADIG_PFD4_STABLE		(1 << 6)
+#define MXC_ANADIG_PFD4_FRAC_OFFSET	0
+
+#define MXC_ANADIG_APLL_LOCK		(1 << 31)
+#define MXC_ANADIG_APLL_FORCE_LOCK	(1 << 30)
+#define MXC_ANADIG_PFD_DIS_OFFSET	16
+#define MXC_ANADIG_PFD_DIS_MASK		0xff
+#define MXC_ANADIG_APLL_LOCK_CNT_OFFSET	0
+#define MXC_ANADIG_APLL_LOCK_CNT_MASK	0xffff
+
 /* Register addresses of CCM*/
 #define MXC_CCM_CCR		(MXC_CCM_BASE + 0x00)
 #define MXC_CCM_CCDR		(MXC_CCM_BASE + 0x04)
@@ -116,6 +156,22 @@ extern void __iomem *pll4_base;
 #define MXC_CCM_CCGR6		(MXC_CCM_BASE + 0x80)
 #define MXC_CCM_CCGR7		(MXC_CCM_BASE + 0x84)
 #define MXC_CCM_CMEOR		(MXC_CCM_BASE + 0x88)
+#define MXC_CCM_CSR2		(MXC_CCM_BASE + 0x8C)
+#define MXC_CCM_CLKSEQ_BYPASS	(MXC_CCM_BASE + 0x90)
+#define MXC_CCM_CLK_SYS		(MXC_CCM_BASE + 0x94)
+#define MXC_CCM_CLK_DDR		(MXC_CCM_BASE + 0x98)
+#define MXC_CCM_ELCDIFPIX	(MXC_CCM_BASE + 0x9C)
+#define MXC_CCM_EPDCPIX		(MXC_CCM_BASE + 0xA0)
+#define MXC_CCM_DISPLAY_AXI	(MXC_CCM_BASE + 0xA4)
+#define MXC_CCM_EPDC_AXI	(MXC_CCM_BASE + 0xA8)
+#define MXC_CCM_GPMI		(MXC_CCM_BASE + 0xAC)
+#define MXC_CCM_BCH		(MXC_CCM_BASE + 0xB0)
+#define MXC_CCM_MSHC_XMSCKI	(MXC_CCM_BASE + 0xB4)
+
+/* CCM Register Offsets. */
+#define MXC_CCM_CDCR_OFFSET		0x4C
+#define MXC_CCM_CACRR_OFFSET		0x10
+#define MXC_CCM_CDHIPR_OFFSET	0x48
 
 /* Define the bits in register CCR */
 #define MXC_CCM_CCR_COSC_EN		(1 << 12)
@@ -149,8 +205,11 @@ extern void __iomem *pll4_base;
 #define MXC_CCM_CSR_REF_EN_B		(1 << 0)
 
 /* Define the bits in register CCSR */
-#define MXC_CCM_CCSR_LP_APM_SEL		(0x1 << 9)
-#define MXC_CCM_CCSR_LP_APM_SEL_MX53		(0x1 << 10)
+#define MXC_CCM_CCSR_PLL3_PFD_EN		(0x1 << 13)
+#define MXC_CCM_CCSR_PLL2_PFD_EN		(0x1 << 12)
+#define MXC_CCM_CCSR_PLL1_PFD_EN		(0x1 << 11)
+#define MXC_CCM_CCSR_LP_APM_SEL			(0x1 << 10)
+#define MXC_CCM_CCSR_LP_APM_SE_MX51L		(0x1 << 9)
 #define MXC_CCM_CCSR_PLL4_SW_CLK_SEL		(1 << 9)
 #define MXC_CCM_CCSR_STEP_SEL_OFFSET		(7)
 #define MXC_CCM_CCSR_STEP_SEL_MASK		(0x3 << 7)
@@ -167,12 +226,17 @@ extern void __iomem *pll4_base;
 #define MXC_CCM_CACRR_ARM_PODF_MASK		(0x7)
 
 /* Define the bits in register CBCDR */
+#define MX50_CCM_CBCDR_WEIM_CLK_SEL		(0x1 << 27)
 #define MXC_CCM_CBCDR_EMI_CLK_SEL			(0x1 << 26)
 #define MXC_CCM_CBCDR_PERIPH_CLK_SEL			(0x1 << 25)
+#define MX50_CCM_CBCDR_PERIPH_CLK_SEL_OFFSET	(25)
+#define MX50_CCM_CBCDR_PERIPH_CLK_SEL_MASK	(0x3 << 25)
 #define MXC_CCM_CBCDR_DDR_HF_SEL_OFFSET		(30)
 #define MXC_CCM_CBCDR_DDR_HF_SEL			(0x1 << 30)
 #define MXC_CCM_CBCDR_DDR_PODF_OFFSET		(27)
-#define MXC_CCM_CBCDR_DDR_PODF_MASK			(0x7 << 27)
+#define MXC_CCM_CBCDR_DDR_PODF_MASK		(0x7 << 27)
+#define MX50_CCM_CBCDR_WEIM_PODF_OFFSET	(22)
+#define MX50_CCM_CBCDR_WEIM_PODF_MASK		(0x7 << 22)
 #define MXC_CCM_CBCDR_EMI_PODF_OFFSET		(22)
 #define MXC_CCM_CBCDR_EMI_PODF_MASK			(0x7 << 22)
 #define MXC_CCM_CBCDR_AXI_B_PODF_OFFSET		(19)
@@ -209,6 +273,8 @@ extern void __iomem *pll4_base;
 #define MXC_CCM_CBCMR_GPU_CLK_SEL_MASK		(0x3 << 4)
 #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET        (14)
 #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK      (0x3 << 14)
+#define MXC_CCM_CBCMR_DBG_APB_CLK_SEL_OFFSET   (2)
+#define MXC_CCM_CBCMR_DBG_APB_CLK_SEL_MASK     (0x3 << 2)
 #define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL		(0x1 << 1)
 #define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL		(0x1 << 0)
 
@@ -228,6 +294,12 @@ extern void __iomem *pll4_base;
 #define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL_MX51		(0x1 << 19)
 #define MXC_CCM_CSCMR1_ESDHC2_CLK_SEL			(0x1 << 19)
 #define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL			(0x1 << 18)
+#define MX50_CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET	(21)
+#define MX50_CCM_CSCMR1_ESDHC1_CLK_SEL_MASK	(0x3 << 21)
+#define MX50_CCM_CSCMR1_ESDHC2_CLK_SEL			(0x1 << 20)
+#define MX50_CCM_CSCMR1_ESDHC4_CLK_SEL			(0x1 << 19)
+#define MX50_CCM_CSCMR1_ESDHC3_CLK_SEL_OFFSET	(16)
+#define MX50_CCM_CSCMR1_ESDHC3_CLK_SEL_MASK		(0x7 << 16)
 #define MXC_CCM_CSCMR1_ESDHC3_MSHC2_CLK_SEL_OFFSET	(16)
 #define MXC_CCM_CSCMR1_ESDHC3_MSHC2_CLK_SEL_MASK		(0x3 << 16)
 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET			(14)
@@ -279,11 +351,11 @@ extern void __iomem *pll4_base;
 #define MXC_CCM_CSCMR2_SLIMBUS_COM			(0x1 << 9)
 #define MXC_CCM_CSCMR2_SLIMBUS_CLK_SEL_OFFSET	(6)
 #define MXC_CCM_CSCMR2_SLIMBUS_CLK_SEL_MASK		(0x7 << 6)
-/* MX51 */
-#define MXC_CCM_CSCMR2_LBD_DI1_IPU_DIV			(0x1 << 11)
-#define MXC_CCM_CSCMR2_LBD_DI0_IPU_DIV			(0x1 << 10)
-#define MXC_CCM_CSCMR2_LBD_DI1_CLK_SEL			(0x1 << 9)
-#define MXC_CCM_CSCMR2_LBD_DI0_CLK_SEL			(0x1 << 8)
+/* MX53 */
+#define MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV			(0x1 << 11)
+#define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV			(0x1 << 10)
+#define MXC_CCM_CSCMR2_LDB_DI1_CLK_SEL			(0x1 << 9)
+#define MXC_CCM_CSCMR2_LDB_DI0_CLK_SEL			(0x1 << 8)
 #define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET		(6)
 #define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK		(0x3 << 6)
 #define MXC_CCM_CSCMR2_SPDIF1_COM			(1 << 5)
@@ -439,6 +511,9 @@ extern void __iomem *pll4_base;
 #define MXC_CCM_CDHIPR_AXI_A_PODF_BUSY			(1 << 0)
 
 /* Define the bits in register CDCR */
+#define MX50_CCM_CDCR_SW_PERIPH_CLK_DIV_REQ_STATUS	(0x1 << 7)
+#define MX50_CCM_CDCR_SW_PERIPH_CLK_DIV_REQ		(0x1 << 6)
+#define MX50_CCM_CDCR_SW_DVFS_EN				(0x1 << 5)
 #define MXC_CCM_CDCR_ARM_FREQ_SHIFT_DIVIDER			(0x1 << 2)
 #define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_OFFSET		(0)
 #define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_MASK		(0x3)
@@ -453,9 +528,10 @@ extern void __iomem *pll4_base;
 #define MXC_CCM_CLPCR_BYPASS_CAN2_LPM_HS			(0x1 << 27)
 #define MXC_CCM_CLPCR_BYPASS_CAN1_LPM_HS			(0x1 << 27)
 #define MXC_CCM_CLPCR_BYPASS_SCC_LPM_HS_MX53			(0x1 << 26)
-#define MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS_MX53			(0x1 << 25)
-#define MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS_MX53			(0x1 << 24)
+#define MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS			(0x1 << 25)
+#define MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS			(0x1 << 24)
 #define MXC_CCM_CLPCR_BYPASS_EMI_INT2_LPM_HS		(0x1 << 23)
+#define MX50_CCM_CLPCR_BYPASS_RNGB_LPM_HS		(0x1 << 23)
 #define MXC_CCM_CLPCR_BYPASS_EMI_INT1_LPM_HS		(0x1 << 22)
 #define MXC_CCM_CLPCR_BYPASS_EMI_SLOW_LPM_HS		(0x1 << 21)
 #define MXC_CCM_CLPCR_BYPASS_EMI_FAST_LPM_HS		(0x1 << 20)
@@ -472,12 +548,13 @@ extern void __iomem *pll4_base;
 #define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM		(0x1 << 5)
 #define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET		(3)
 #define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK		(0x3 << 3)
+#define MXC_CCM_CLPCR_BYPASS_PMIC_VFUNC_READY		(0x1 << 2)
 #define MXC_CCM_CLPCR_LPM_OFFSET			(0)
 #define MXC_CCM_CLPCR_LPM_MASK			(0x3)
 
 /* Define the bits in register CISR */
 #define MXC_CCM_CISR_ARM_PODF_LOADED_MX51		(0x1 << 25)
-#define MXC_CCM_CISR_ARM_PODF_LOADED_MX53		(0x1 << 26)
+#define MXC_CCM_CISR_ARM_PODF_LOADED		(0x1 << 26)
 #define MXC_CCM_CISR_TEMP_MON_ALARM				(0x1 << 25)
 #define MXC_CCM_CISR_EMI_CLK_SEL_LOADED			(0x1 << 23)
 #define MXC_CCM_CISR_PER_CLK_SEL_LOADED			(0x1 << 22)
@@ -490,6 +567,7 @@ extern void __iomem *pll4_base;
 #define MXC_CCM_CISR_COSC_READY				(0x1 << 6)
 #define MXC_CCM_CISR_CKIH2_READY				(0x1 << 5)
 #define MXC_CCM_CISR_CKIH_READY				(0x1 << 4)
+#define MX50_CCM_CISR_CAMP1_READY			(0x1 << 4)
 #define MXC_CCM_CISR_FPM_READY				(0x1 << 3)
 #define MXC_CCM_CISR_LRF_PLL3					(0x1 << 2)
 #define MXC_CCM_CISR_LRF_PLL2					(0x1 << 1)
@@ -499,13 +577,14 @@ extern void __iomem *pll4_base;
 #define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED_MX51		(0x1 << 25)
 #define MXC_CCM_CIMR_MASK_EMI_PODF_LOADED_MX51		(0x1 << 20)
 #define MXC_CCM_CIMR_MASK_AXI_C_PODF_LOADED_MX51	(0x1 << 19)
-#define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED_MX53		(0x1 << 26)
+#define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED		(0x1 << 26)
 #define MXC_CCM_CIMR_MASK_TEMP_MON_ALARM		(0x1 << 25)
 #define MXC_CCM_CIMR_MASK_EMI_CLK_SEL_LOADED		(0x1 << 23)
 #define MXC_CCM_CIMR_MASK_PER_CLK_SEL_LOADED		(0x1 << 22)
 #define MXC_CCM_CIMR_MASK_NFC_IPG_INT_MEM_PODF_LOADED	(0x1 << 21)
 #define MXC_CCM_CIMR_MASK_AHB_PODF_LOADED_MX53		(0x1 << 20)
 #define MXC_CCM_CIMR_MASK_EMI_SLOW_PODF_LOADED_MX53		(0x1 << 19)
+#define MX50_CCM_CIMR_MASK_WEIM_PODF_LOADED		(0x1 << 19)
 #define MXC_CCM_CIMR_MASK_AXI_B_PODF_LOADED		(0x1 << 18)
 #define MXC_CCM_CIMR_MASK_AXI_A_PODF_LOADED		(0x1 << 17)
 #define MXC_CCM_CIMR_MASK_DIVIDER_LOADED		(0x1 << 16)
@@ -513,8 +592,8 @@ extern void __iomem *pll4_base;
 #define MXC_CCM_CIMR_MASK_COSC_READY_MX51			(0x1 << 5)
 #define MXC_CCM_CIMR_MASK_CKIH_READY			(0x1 << 4)
 #define MXC_CCM_CIMR_MASK_FPM_READY			(0x1 << 3)
-/* MX53 */
-#define MXC_CCM_CIMR_MASK_COSC_READY_MX53			(0x1 << 6)
+/* MX53/MX50 */
+#define MXC_CCM_CIMR_MASK_COSC_READY			(0x1 << 6)
 #define MXC_CCM_CIMR_MASK_CAMP2_READY			(0x1 << 5)
 #define MXC_CCM_CIMR_MASK_CAMP1_READY			(0x1 << 4)
 #define MXC_CCM_CIMR_MASK_LRF_PLL4			(0x1 << 3)
@@ -542,6 +621,13 @@ extern void __iomem *pll4_base;
 #define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_OFFSET		(0)
 #define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_MASK		(0x7)
 
+#define MX50_CCM_CCOSR_CKO1_SLOW_SEL			(0x1 << 8)
+#define MX50_CCM_CCOSR_CKO1_EN				(0x1 << 7)
+#define MX50_CCM_CCOSR_CKO1_DIV_OFFSET			(4)
+#define MX50_CCM_CCOSR_CKO1_DIV_MASK			(0x7 << 4)
+#define MX50_CCM_CCOSR_CKO1_SEL_OFFSET			(0)
+#define MX50_CCM_CCOSR_CKO1_SEL_MASK			(0xF)
+
 /* Define the bits in registers CCGRx */
 #define MXC_CCM_CCGR_CG_MASK				0x3
 
@@ -729,6 +815,82 @@ extern void __iomem *pll4_base;
 #define MXC_CCM_CCGR7_CG1_OFFSET			2
 #define MXC_CCM_CCGR7_CG0_OFFSET			0
 
+/* Define the bits in registers CSR2  */
+#define MXC_CCM_CSR2_ELCDIF_PIX_BUSY			(0x1 << 9)
+#define MXC_CCM_CSR2_EPDC_PIX_BUSY			(0x1 << 8)
+#define MXC_CCM_CSR2_EPDC_AXI_BUSY			(0x1 << 4)
+#define MXC_CCM_CSR2_DISPLAY_AXI_BUSY			(0x1 << 3)
+
+/* Define the bits in registers CLKSEQ_BYPASS  */
+#define MXC_CCM_CLKSEQ_BYPASS_BYPASS_ELCDIF_PIX_CLK_SEL_OFFSET	14
+#define MXC_CCM_CLKSEQ_BYPASS_BYPASS_ELCDIF_PIX_CLK_SEL_MASK	(0x3 << 14)
+#define MXC_CCM_CLKSEQ_BYPASS_BYPASS_EPDC_PIX_CLK_SEL_OFFSET	12
+#define MXC_CCM_CLKSEQ_BYPASS_BYPASS_EPDC_PIX_CLK_SEL_MASK	(0x3 << 12)
+#define MXC_CCM_CLKSEQ_BYPASS_BYPASS_EPDC_AXI_CLK_SEL_OFFSET	4
+#define MXC_CCM_CLKSEQ_BYPASS_BYPASS_EPDC_AXI_CLK_SEL_MASK	(0x3 << 4)
+#define MXC_CCM_CLKSEQ_BYPASS_BYPASS_DISPLAY_AXI_CLK_SEL_OFFSET	2
+#define MXC_CCM_CLKSEQ_BYPASS_BYPASS_DISPLAY_AXI_CLK_SEL_MASK	(0x3 << 2)
+
+
+/* Define the bits in registers CLK_SYS */
+#define MXC_CCM_CLK_SYS_SYS_XTAL_CLKGATE_OFFSET	(30)
+#define MXC_CCM_CLK_SYS_SYS_XTAL_CLKGATE_MASK	(0x3 << 30)
+#define MXC_CCM_CLK_SYS_SYS_PLL_CLKGATE_OFFSET		(28)
+#define MXC_CCM_CLK_SYS_SYS_PLL_CLKGATE_MASK	(0x3 << 28)
+#define MXC_CCM_CLK_SYS_DIV_XTAL_OFFSET			(6)
+#define MXC_CCM_CLK_SYS_DIV_XTAL_MASK			(0xF << 6)
+#define MXC_CCM_CLK_SYS_DIV_PLL_OFFSET			(0)
+#define MXC_CCM_CLK_SYS_DIV_PLL_MASK				(0x3F)
+
+
+/* Define the bits in registers CLK_DDR */
+#define MXC_CCM_CLK_DDR_DDR_CLKGATE_OFFSET	(30)
+#define MXC_CCM_CLK_DDR_DDR_CLKGATE_MASK	(0x3 << 30)
+#define MXC_CCM_CLK_DDR_DDR_PFD_SEL		(1 << 6)
+#define MXC_CCM_CLK_DDR_DDR_DIV_PLL_OFFSET	(0)
+#define MXC_CCM_CLK_DDR_DDR_DIV_PLL_MASK	(0x3F)
+
+/* Define the bits in register DISPLAY_AXI */
+#define MXC_CCM_DISPLAY_AXI_CLKGATE_OFFSET	(30)
+#define MXC_CCM_DISPLAY_AXI_CLKGATE_MASK	(0x3 << 30)
+#define MXC_CCM_DISPLAY_AXI_DIV_OFFSET		(0)
+#define MXC_CCM_DISPLAY_AXI_DIV_MASK		(0x3F)
+
+/* Define the bits in register EPDC_AXI */
+#define MXC_CCM_EPDC_AXI_CLKGATE_OFFSET	(30)
+#define MXC_CCM_EPDC_AXI_CLKGATE_MASK	(0x3 << 30)
+#define MXC_CCM_EPDC_AXI_DIV_OFFSET		(0)
+#define MXC_CCM_EPDC_AXI_DIV_MASK		(0x3F)
+
+/* Define the bits in register EPDCPIX */
+#define MXC_CCM_EPDC_PIX_CLKGATE_OFFSET		(30)
+#define MXC_CCM_EPDC_PIX_CLKGATE_MASK		(0x3 << 30)
+#define MXC_CCM_EPDC_PIX_CLK_PRED_OFFSET	(12)
+#define MXC_CCM_EPDC_PIX_CLK_PRED_MASK		(0x3 << 12)
+#define MXC_CCM_EPDC_PIX_CLK_PODF_OFFSET	(0)
+#define MXC_CCM_EPDC_PIX_CLK_PODF_MASK		(0xFFF)
+
+/* Define the bits in register ELCDIFPIX */
+#define MXC_CCM_ELCDIFPIX_CLKGATE_OFFSET	(30)
+#define MXC_CCM_ELCDIFPIX_CLKGATE_MASK		(0x3 << 30)
+#define MXC_CCM_ELCDIFPIX_CLK_PRED_OFFSET	(12)
+#define MXC_CCM_ELCDIFPIX_CLK_PRED_MASK		(0x3 << 12)
+#define MXC_CCM_ELCDIFPIX_CLK_PODF_OFFSET	(0)
+#define MXC_CCM_ELCDIFPIX_CLK_PODF_MASK		(0xFFF)
+
+
+/* Define the bits in register GPMI */
+#define MXC_CCM_GPMI_CLKGATE_OFFSET		(30)
+#define MXC_CCM_GPMI_CLKGATE_MASK		(0x3 << 30)
+#define MXC_CCM_GPMI_CLK_DIV_OFFSET		(0)
+#define MXC_CCM_GPMI_CLK_DIV_MASK		(0x3F)
+
+/* Define the bits in register BCH */
+#define MXC_CCM_BCH_CLKGATE_OFFSET		(30)
+#define MXC_CCM_BCH_CLKGATE_MASK		(0x3 << 30)
+#define MXC_CCM_BCH_CLK_DIV_OFFSET		(0)
+#define MXC_CCM_BCH_CLK_DIV_MASK		(0x3F)
+
 #define MXC_GPC_BASE		(IO_ADDRESS(GPC_BASE_ADDR))
 #define MXC_DPTC_LP_BASE	(MXC_GPC_BASE + 0x80)
 #define MXC_DPTC_GP_BASE	(MXC_GPC_BASE + 0x100)
@@ -787,11 +949,12 @@ extern void __iomem *arm_plat_base;
 #define MXC_DVFSPER_PMCR1	(MXC_DVFS_PER_BASE + 0x1C)
 
 /* GPC */
-#define MXC_GPC_CNTR		(MXC_GPC_BASE + 0x0)
-#define MXC_GPC_PGR		(MXC_GPC_BASE + 0x4)
-#define MXC_GPC_VCR		(MXC_GPC_BASE + 0x8)
-#define MXC_GPC_ALL_PU		(MXC_GPC_BASE + 0xC)
-#define MXC_GPC_NEON		(MXC_GPC_BASE + 0x10)
+#define MXC_GPC_CNTR				(MXC_GPC_BASE  + 0x0)
+#define MXC_GPC_PGR				(MXC_GPC_BASE  + 0x4)
+#define MXC_GPC_VCR				(MXC_GPC_BASE  + 0x8)
+#define MXC_GPC_CNTR_OFFSET		0x0
+#define MXC_GPC_PGR_OFFSET		0x4
+#define MXC_GPC_VCR_OFFSET		0x8
 
 /* PGC */
 #define MXC_PGC_IPU_PGCR	(MXC_PGC_IPU_BASE + 0x0)