diff options
| author | Dinh Nguyen <Dinh.Nguyen@freescale.com> | 2010-03-18 14:43:02 -0500 |
|---|---|---|
| committer | Alejandro Gonzalez <alex.gonzalez@digi.com> | 2010-05-25 11:20:13 +0200 |
| commit | fe5f8e57cebd49332675067f969ed232465abb4c (patch) | |
| tree | 6a0578101cae1e0bf119a30acb9df66553852907 /arch/arm/mach-mx5 | |
| parent | cfd568c81b246f5adca17a84ceaeaff03f558d41 (diff) | |
ENGR00121109 MX53: Add MSL layer
Added MSL layer for MX53 with changes in MX51 for single kernel boot
support.
Added CCGR clocking changes.
Fixed SDHC clock dependencies.
Fix emi_intr clocks and fix warnings in clock code.
Signed-off-by: Rob Herring <r.herring@freescale.com>
Signed-off-by: Lily Zhang <r58066@freescale.com>
Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
Signed-off-by: Ranjani Vaidyanathan-RA5478 <Ranjani.Vaidyanathan@freescale.com>
Signed-off-by: Dinh Nguyen <Dinh.Nguyen@freescale.com>
Signed-off-by: Alejandro Gonzalez <alex.gonzalez@digi.com>
Diffstat (limited to 'arch/arm/mach-mx5')
28 files changed, 5041 insertions, 756 deletions
diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig index 9dc1d3a02b18..e7bc97f9fcd1 100644 --- a/arch/arm/mach-mx5/Kconfig +++ b/arch/arm/mach-mx5/Kconfig @@ -1,9 +1,10 @@ -menu "MX5 Options" - depends on ARCH_MX5 +if ARCH_MX5 config ARCH_MX51 - bool "Support MX51 based platforms" - default y + bool + +config ARCH_MX53 + bool config FORCE_MAX_ZONEORDER int "MAX_ORDER" @@ -17,20 +18,28 @@ config MX5_OPTIONS select MXC_TZIC config MACH_MX51_3DS - bool "Support MX51 3-Stack platforms" - default y - depends on ARCH_MX51 + bool "Support MX51 3-Stack platform" + select ARCH_MX51 help Include support for MX51 3-Stack platform. This includes specific configurations for the board and its peripherals. config MACH_MX51_BABBAGE - bool "Support MX51 BABBAGE platforms" - depends on ARCH_MX51 + bool "Support MX51 BABBAGE platform" + select ARCH_MX51 help Include support for MX51 Babbage platform. This includes specific configurations for the board and its peripherals. +config MACH_MX53_EVK + bool "Support MX53 EVK platform" + select ARCH_MX53 + help + Include support for MX53 EVK platform. This includes specific + configurations for the board and its peripherals. + +comment "MX5x Options:" + config MXC_SDMA_API bool "Use SDMA API" default y @@ -60,4 +69,4 @@ config SDMA_IRAM help Support Internal RAM as SDMA buffer or control structures -endmenu +endif diff --git a/arch/arm/mach-mx5/Makefile b/arch/arm/mach-mx5/Makefile index 1e94b4cc4233..cbf2137fd938 100644 --- a/arch/arm/mach-mx5/Makefile +++ b/arch/arm/mach-mx5/Makefile @@ -10,4 +10,5 @@ sdram_autogating.o bus_freq.o usb_dr.o usb_h1.o usb_h2.o dummy_gpio.o wfi.o susp obj-$(CONFIG_MACH_MX51_3DS) += mx51_3stack.o mx51_3stack_gpio.o mx51_3stack_pmic_mc13892.o obj-$(CONFIG_MACH_MX51_BABBAGE) += mx51_babbage.o mx51_babbage_gpio.o mx51_babbage_pmic_mc13892.o +obj-$(CONFIG_MACH_MX53_EVK) += mx53_evk.o mx53_evk_gpio.o mx53_evk_pmic_mc13892.o diff --git a/arch/arm/mach-mx5/Makefile.boot b/arch/arm/mach-mx5/Makefile.boot index 9939a19d99a1..741f60437582 100644 --- a/arch/arm/mach-mx5/Makefile.boot +++ b/arch/arm/mach-mx5/Makefile.boot @@ -1,3 +1,6 @@ - zreladdr-y := 0x90008000 -params_phys-y := 0x90000100 -initrd_phys-y := 0x90800000 + zreladdr-$(CONFIG_ARCH_MX51) := 0x90008000 +params_phys-$(CONFIG_ARCH_MX51) := 0x90000100 +initrd_phys-$(CONFIG_ARCH_MX51) := 0x90800000 + zreladdr-$(CONFIG_ARCH_MX53) := 0x70008000 +params_phys-$(CONFIG_ARCH_MX53) := 0x70000100 +initrd_phys-$(CONFIG_ARCH_MX53) := 0x70800000 diff --git a/arch/arm/mach-mx5/board-mx53_evk.h b/arch/arm/mach-mx5/board-mx53_evk.h new file mode 100644 index 000000000000..14d13827c7bd --- /dev/null +++ b/arch/arm/mach-mx5/board-mx53_evk.h @@ -0,0 +1,98 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ASM_ARCH_MXC_BOARD_MX53_EVK_H__ +#define __ASM_ARCH_MXC_BOARD_MX53_EVK_H__ + +/*! + * @defgroup BRDCFG_MX53 Board Configuration Options + * @ingroup MSL_MX53 + */ + +/*! + * @file mach-mx53/board-mx53_evk.h + * + * @brief This file contains all the board level configuration options. + * + * It currently hold the options defined for MX53 EVK Platform. + * + * @ingroup BRDCFG_MX53 + */ + +/* + * Include Files + */ +#include <mach/mxc_uart.h> + +/*! + * @name MXC UART board level configurations + */ +/*! @{ */ +/*! + * Specifies if the Irda transmit path is inverting + */ +#define MXC_IRDA_TX_INV 0 +/*! + * Specifies if the Irda receive path is inverting + */ +#define MXC_IRDA_RX_INV 0 + +/* UART 1 configuration */ +/*! + * This define specifies if the UART port is configured to be in DTE or + * DCE mode. There exists a define like this for each UART port. Valid + * values that can be used are \b MODE_DTE or \b MODE_DCE. + */ +#define UART1_MODE MODE_DCE +/*! + * This define specifies if the UART is to be used for IRDA. There exists a + * define like this for each UART port. Valid values that can be used are + * \b IRDA or \b NO_IRDA. + */ +#define UART1_IR NO_IRDA +/*! + * This define is used to enable or disable a particular UART port. If + * disabled, the UART will not be registered in the file system and the user + * will not be able to access it. There exists a define like this for each UART + * port. Specify a value of 1 to enable the UART and 0 to disable it. + */ +#define UART1_ENABLED 1 +/*! @} */ +/* UART 2 configuration */ +#define UART2_MODE MODE_DCE +#define UART2_IR IRDA +#define UART2_ENABLED 1 +/* UART 3 configuration */ +#define UART3_MODE MODE_DTE +#define UART3_IR NO_IRDA +#define UART3_ENABLED 1 +/* UART 4 configuration */ +#define UART4_MODE MODE_DCE +#define UART4_IR NO_IRDA +#define UART4_ENABLED 1 +/* UART 5 configuration */ +#define UART5_MODE MODE_DCE +#define UART5_IR NO_IRDA +#define UART5_ENABLED 1 + +#define MXC_LL_UART_PADDR UART1_BASE_ADDR +#define MXC_LL_UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR) + +extern int __init mx53_evk_init_mc13892(void); + +#endif /* __ASM_ARCH_MXC_BOARD_MX53_EVK_H__ */ diff --git a/arch/arm/mach-mx5/bus_freq.c b/arch/arm/mach-mx5/bus_freq.c index ae90f0338ed0..ce265fcff89e 100644 --- a/arch/arm/mach-mx5/bus_freq.c +++ b/arch/arm/mach-mx5/bus_freq.c @@ -94,7 +94,6 @@ struct dvfs_wp dvfs_core_setpoint[] = { int set_low_bus_freq(void) { - struct clk *tclk; u32 reg; if (busfreq_suspended) @@ -153,7 +152,6 @@ int set_low_bus_freq(void) int set_high_bus_freq(int high_bus_freq) { u32 reg; - struct clk *tclk; if (bus_freq_scaling_initialized) { stop_sdram_autogating(); diff --git a/arch/arm/mach-mx5/clock.c b/arch/arm/mach-mx5/clock.c index fe39bced5000..184e8772ce16 100644 --- a/arch/arm/mach-mx5/clock.c +++ b/arch/arm/mach-mx5/clock.c @@ -34,11 +34,12 @@ static struct clk pll1_main_clk; static struct clk pll1_sw_clk; static struct clk pll2_sw_clk; static struct clk pll3_sw_clk; +static struct clk pll4_sw_clk; static struct clk lp_apm_clk; static struct clk tve_clk; static struct clk emi_fast_clk; static struct clk emi_slow_clk; -static struct clk emi_intr_clk; +static struct clk emi_intr_clk[]; static struct clk ddr_clk; static struct clk ipu_clk[]; static struct clk axi_a_clk; @@ -54,6 +55,7 @@ static struct cpu_wp *cpu_wp_tbl; void __iomem *pll1_base; void __iomem *pll2_base; void __iomem *pll3_base; +void __iomem *pll4_base; int cpu_wp_nr; int lp_high_freq; @@ -71,6 +73,8 @@ extern void propagate_rate(struct clk *tclk); struct cpu_wp *(*get_cpu_wp)(int *wp); void (*set_num_cpu_wp)(int num); +static struct clk esdhc3_clk[]; + static void __calc_pre_post_dividers(u32 div, u32 *pre, u32 *post) { u32 min_pre, temp_pre, old_err, err; @@ -199,6 +203,8 @@ static inline void __iomem *_get_pll_base(struct clk *pll) return pll2_base; else if (pll == &pll3_sw_clk) return pll3_base; + else if (pll == &pll4_sw_clk) + return pll4_base; else BUG(); @@ -524,6 +530,17 @@ static struct clk pll3_sw_clk = { .flags = RATE_PROPAGATES, }; +/* same as pll4_main_clk. These two clocks should always be the same */ +static struct clk pll4_sw_clk = { + .name = "pll4", + .parent = &osc_clk, + .set_rate = _clk_pll_set_rate, + .recalc = _clk_pll_recalc, + .enable = _clk_pll_enable, + .disable = _clk_pll_disable, + .flags = RATE_PROPAGATES, +}; + static int _clk_lp_apm_set_parent(struct clk *clk, struct clk *parent) { u32 reg; @@ -954,7 +971,10 @@ static int _clk_max_enable(struct clk *clk) /* Handshake with MAX when LPM is entered. */ reg = __raw_readl(MXC_CCM_CLPCR); - reg &= ~MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS; + if (cpu_is_mx51()) + reg &= ~MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS_MX51; + else + reg &= ~MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS_MX53; __raw_writel(reg, MXC_CCM_CLPCR); return 0; @@ -969,7 +989,10 @@ static void _clk_max_disable(struct clk *clk) /* No Handshake with MAX when LPM is entered as its disabled. */ reg = __raw_readl(MXC_CCM_CLPCR); - reg |= MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS; + if (cpu_is_mx51()) + reg |= MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS_MX51; + else + reg |= MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS_MX53; __raw_writel(reg, MXC_CCM_CLPCR); } @@ -1109,14 +1132,27 @@ static struct clk emi_fast_clk = { .disable = _clk_disable_inwait, }; -static struct clk emi_intr_clk = { +static struct clk emi_intr_clk[] = { + { .name = "emi_intr_clk", + .id = 0, .parent = &ahb_clk, .secondary = &ahbmux2_clk, .enable_reg = MXC_CCM_CCGR5, .enable_shift = MXC_CCM_CCGR5_CG9_OFFSET, .enable = _clk_enable, .disable = _clk_disable_inwait, + }, + { + .name = "emi_intr_clk", + .id = 1, + .parent = &ahb_clk, + .secondary = &ahbmux2_clk, + .enable_reg = MXC_CCM_CCGR6, + .enable_shift = MXC_CCM_CCGR6_CG4_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable_inwait, + } }; static void _clk_ipg_recalc(struct clk *clk) @@ -1219,6 +1255,23 @@ static struct clk ipumux2_clk = { .disable = _clk_ipmux_disable, }; +static int _clk_ocram_enable(struct clk *clk) +{ + return 0; +} + +static void _clk_ocram_disable(struct clk *clk) +{ +} + +static struct clk ocram_clk = { + .name = "ocram_clk", + .enable_reg = MXC_CCM_CCGR6, + .enable_shift = MXC_CCM_CCGR6_CG1_OFFSET, + .enable = _clk_ocram_enable, + .disable = _clk_ocram_disable, +}; + static struct clk aips_tz1_clk = { .name = "aips_tz1_clk", @@ -1256,7 +1309,10 @@ static int _clk_sdma_enable(struct clk *clk) /* Handshake with SDMA when LPM is entered. */ reg = __raw_readl(MXC_CCM_CLPCR); - reg &= ~MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS; + if (cpu_is_mx51()) + reg &= ~MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS_MX51; + else + reg &= ~MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS_MX53; __raw_writel(reg, MXC_CCM_CLPCR); return 0; @@ -1269,7 +1325,10 @@ static void _clk_sdma_disable(struct clk *clk) _clk_disable(clk); /* No handshake with SDMA as its not enabled. */ reg = __raw_readl(MXC_CCM_CLPCR); - reg |= MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS; + if (cpu_is_mx51()) + reg |= MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS_MX51; + else + reg |= MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS_MX53; __raw_writel(reg, MXC_CCM_CLPCR); } @@ -1287,7 +1346,7 @@ static struct clk sdma_clk[] = { .name = "sdma_ipg_clk", .parent = &ipg_clk, #ifdef CONFIG_SDMA_IRAM - .secondary = &emi_intr_clk, + .secondary = &emi_intr_clk[0], #endif }, }; @@ -1324,7 +1383,10 @@ static void _clk_ipu_disable(struct clk *clk) /* No handshake with IPU whe dividers are changed * as its not enabled. */ reg = __raw_readl(MXC_CCM_CCDR); - reg |= MXC_CCM_CCDR_IPU_HS_MASK; + if (cpu_is_mx51()) + reg |= MXC_CCM_CCDR_IPU_HS_MASK; + else + reg |= MXC_CCM_CCDR_IPU_HS_MX53_MASK; __raw_writel(reg, MXC_CCM_CCDR); /* No handshake with IPU when LPM is entered as its not enabled. */ @@ -1378,7 +1440,11 @@ static int _clk_ipu_di_set_parent(struct clk *clk, struct clk *parent) reg |= 1 << MXC_CCM_CSCMR2_DI_CLK_SEL_OFFSET(clk->id); else if (parent == &ckih_clk) reg |= 2 << MXC_CCM_CSCMR2_DI_CLK_SEL_OFFSET(clk->id); - else if (parent == &tve_clk) + else if ((parent == &pll4_sw_clk) && (clk->id == 0)) { + if (cpu_is_mx51()) + return -EINVAL; + reg |= 3 << MXC_CCM_CSCMR2_DI_CLK_SEL_OFFSET(clk->id); + } else if ((parent == &tve_clk) && (clk->id == 1)) reg |= 3 << MXC_CCM_CSCMR2_DI_CLK_SEL_OFFSET(clk->id); else /* Assume any other clock is external clock pin */ reg |= 4 << MXC_CCM_CSCMR2_DI_CLK_SEL_OFFSET(clk->id); @@ -1396,11 +1462,16 @@ static void _clk_ipu_di_recalc(struct clk *clk) MXC_CCM_CSCMR2_DI_CLK_SEL_OFFSET(clk->id); if (mux == 0) { reg = __raw_readl(MXC_CCM_CDCDR) & - MXC_CCM_CDCDR_DI_CLK_PRED_MASK; - div = (reg >> MXC_CCM_CDCDR_DI_CLK_PRED_OFFSET) + 1; + MXC_CCM_CDCDR_DI1_CLK_PRED_MASK; + div = (reg >> MXC_CCM_CDCDR_DI1_CLK_PRED_OFFSET) + 1; clk->rate = clk->parent->rate / div; - } else if (mux == 3) { + } else if ((mux == 3) && (clk->id == 1)) { clk->rate = clk->parent->rate / 8; + } else if ((mux == 3) && (clk->id == 0)) { + reg = __raw_readl(MXC_CCM_CDCDR) & + MXC_CCM_CDCDR_DI_PLL4_PODF_MASK; + div = (reg >> MXC_CCM_CDCDR_DI_PLL4_PODF_OFFSET) + 1; + clk->rate = clk->parent->rate / div; } else { clk->rate = clk->parent->rate; } @@ -1416,10 +1487,20 @@ static int _clk_ipu_di_set_rate(struct clk *clk, unsigned long rate) if (((clk->parent->rate / div) != rate) || (div > 8)) return -EINVAL; - reg = __raw_readl(MXC_CCM_CDCDR); - reg &= ~MXC_CCM_CDCDR_DI_CLK_PRED_MASK; - reg |= (div - 1) << MXC_CCM_CDCDR_DI_CLK_PRED_OFFSET; - __raw_writel(reg, MXC_CCM_CDCDR); + if ((clk->parent == &pll4_sw_clk) && (clk->id == 0)) { + reg = __raw_readl(MXC_CCM_CDCDR); + reg &= ~MXC_CCM_CDCDR_DI_PLL4_PODF_MASK; + reg |= (div - 1) << MXC_CCM_CDCDR_DI_PLL4_PODF_OFFSET; + __raw_writel(reg, MXC_CCM_CDCDR); + } else if (clk->parent == &pll3_sw_clk) { + reg = __raw_readl(MXC_CCM_CDCDR); + reg &= ~MXC_CCM_CDCDR_DI1_CLK_PRED_MASK; + reg |= (div - 1) << MXC_CCM_CDCDR_DI1_CLK_PRED_OFFSET; + __raw_writel(reg, MXC_CCM_CDCDR); + } else if ((clk->parent == &tve_clk) && (clk->id == 1)) + clk->rate = rate; /*the rate decided by tve hw actually*/ + else + return -EINVAL; clk->rate = rate; @@ -1692,14 +1773,16 @@ static int _clk_tve_set_parent(struct clk *clk, struct clk *parent) reg = __raw_readl(MXC_CCM_CSCMR1); - if (parent == &pll3_sw_clk) { + if ((parent == &pll3_sw_clk) && cpu_is_mx51()) { reg &= ~(MXC_CCM_CSCMR1_TVE_CLK_SEL); - } else if (parent == &osc_clk) { + } else if ((parent == &pll4_sw_clk) && cpu_is_mx53()) { + reg &= ~(MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL); + } else if ((parent == &osc_clk) && cpu_is_mx51()) { reg |= MXC_CCM_CSCMR1_TVE_CLK_SEL; - reg &= MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL; + reg &= ~MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL; } else if (parent == &ckih_clk) { - reg |= MXC_CCM_CSCMR1_TVE_CLK_SEL; reg |= MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL; + reg |= MXC_CCM_CSCMR1_TVE_CLK_SEL; /* Reserved on MX53 */ } else { BUG(); } @@ -1713,7 +1796,7 @@ static void _clk_tve_recalc(struct clk *clk) u32 reg, div; reg = __raw_readl(MXC_CCM_CSCMR1); - if ((reg & MXC_CCM_CSCMR1_TVE_CLK_SEL) == 0) { + if ((reg & (MXC_CCM_CSCMR1_TVE_CLK_SEL | MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL)) == 0) { reg = __raw_readl(MXC_CCM_CDCDR) & MXC_CCM_CDCDR_TVE_CLK_PRED_MASK; div = (reg >> MXC_CCM_CDCDR_TVE_CLK_PRED_OFFSET) + 1; @@ -1729,7 +1812,9 @@ static unsigned long _clk_tve_round_rate(struct clk *clk, u32 reg, div; reg = __raw_readl(MXC_CCM_CSCMR1); - if (reg & MXC_CCM_CSCMR1_TVE_CLK_SEL) + if (cpu_is_mx51() && (reg & MXC_CCM_CSCMR1_TVE_CLK_SEL)) + return -EINVAL; + if (cpu_is_mx53() && (reg & MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL)) return -EINVAL; div = clk->parent->rate / rate; @@ -1745,7 +1830,9 @@ static int _clk_tve_set_rate(struct clk *clk, unsigned long rate) u32 reg, div; reg = __raw_readl(MXC_CCM_CSCMR1); - if (reg & MXC_CCM_CSCMR1_TVE_CLK_SEL) + if (cpu_is_mx51() && (reg & MXC_CCM_CSCMR1_TVE_CLK_SEL)) + return -EINVAL; + if (cpu_is_mx53() && (reg & MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL)) return -EINVAL; div = clk->parent->rate / rate; @@ -1777,9 +1864,9 @@ static void _clk_tve_disable(struct clk *clk) { _clk_disable(clk); if (clk_get_parent(&ipu_di_clk[1]) == clk) { + clk_disable(&ipu_di_clk[1]); ipu_di_clk[1].set_parent(&ipu_di_clk[1], &pll3_sw_clk); ipu_di_clk[1].parent = &pll3_sw_clk; - clk_disable(&ipu_di_clk[1]); } } @@ -1922,6 +2009,80 @@ static struct clk uart3_clk[] = { }, }; +static struct clk uart4_clk[] = { + { + .name = "uart_clk", + .id = 3, + .parent = &uart_main_clk, + .secondary = &uart4_clk[1], + .enable_reg = MXC_CCM_CCGR7, + .enable_shift = MXC_CCM_CCGR7_CG5_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, +#ifdef UART4_DMA_ENABLE + .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE, +#endif + }, + { + .name = "uart_ipg_clk", + .id = 3, + .parent = &ipg_clk, + .secondary = &spba_clk, + .enable_reg = MXC_CCM_CCGR7, + .enable_shift = MXC_CCM_CCGR7_CG4_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, +}; + +static struct clk uart5_clk[] = { + { + .name = "uart_clk", + .id = 4, + .parent = &uart_main_clk, + .secondary = &uart5_clk[1], + .enable_reg = MXC_CCM_CCGR7, + .enable_shift = MXC_CCM_CCGR7_CG7_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, +#ifdef UART5_DMA_ENABLE + .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE, +#endif + }, + { + .name = "uart_ipg_clk", + .id = 4, + .parent = &ipg_clk, + .secondary = &spba_clk, + .enable_reg = MXC_CCM_CCGR7, + .enable_shift = MXC_CCM_CCGR7_CG6_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, +}; + +static struct clk esai_clk[] = { + { + .name = "esai_clk", + .id = 2, + .parent = &pll3_sw_clk, + .secondary = &esai_clk[1], + .enable_reg = MXC_CCM_CCGR6, + .enable_shift = MXC_CCM_CCGR6_CG9_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, + { + .name = "esai_ipg_clk", + .id = 2, + .parent = &pll3_sw_clk, + .enable_reg = MXC_CCM_CCGR6, + .enable_shift = MXC_CCM_CCGR6_CG8_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, +}; + static struct clk gpt_clk[] = { { .name = "gpt_clk", @@ -2022,6 +2183,15 @@ static struct clk i2c_clk[] = { .enable = _clk_enable, .disable = _clk_disable, }, + { + .name = "i2c_clk", + .id = 2, + .parent = &ipg_perclk, + .enable_reg = MXC_CCM_CCGR1, + .enable_shift = MXC_CCM_CCGR1_CG11_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, }; static void _clk_hsi2c_serial_recalc(struct clk *clk) @@ -2235,7 +2405,7 @@ static struct clk ssi1_clk[] = { .id = 0, .parent = &aips_tz2_clk, #ifdef CONFIG_SND_MXC_SOC_IRAM - .secondary = &emi_intr_clk, + .secondary = &emi_intr_clk[0], #else .secondary = &emi_fast_clk, #endif @@ -2298,7 +2468,7 @@ static struct clk ssi2_clk[] = { .id = 1, .parent = &spba_clk, #ifdef CONFIG_SND_MXC_SOC_IRAM - .secondary = &emi_intr_clk, + .secondary = &emi_intr_clk[0], #else .secondary = &emi_fast_clk, #endif @@ -2323,6 +2493,26 @@ static void _clk_ssi_ext1_recalc(struct clk *clk) } } +static int _clk_ssi_ext1_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg, div; + + div = clk->parent->rate / rate; + if (div == 0) + div++; + if (((clk->parent->rate / div) != rate) || (div > 8)) + return -EINVAL; + + reg = __raw_readl(MXC_CCM_CS1CDR); + reg &= ~MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_MASK; + reg |= (div - 1) << MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_OFFSET; + __raw_writel(reg, MXC_CCM_CS1CDR); + + clk->rate = rate; + + return 0; +} + static int _clk_ssi_ext1_set_parent(struct clk *clk, struct clk *parent) { u32 reg, mux; @@ -2343,10 +2533,25 @@ static int _clk_ssi_ext1_set_parent(struct clk *clk, struct clk *parent) return 0; } +static unsigned long _clk_ssi_ext1_round_rate(struct clk *clk, + unsigned long rate) +{ + u32 div; + + div = clk->parent->rate / rate; + if (div > 8) + div = 8; + else if (div == 0) + div++; + return clk->parent->rate / div; +} + static struct clk ssi_ext1_clk = { .name = "ssi_ext1_clk", .parent = &pll3_sw_clk, .set_parent = _clk_ssi_ext1_set_parent, + .set_rate = _clk_ssi_ext1_set_rate, + .round_rate = _clk_ssi_ext1_round_rate, .recalc = _clk_ssi_ext1_recalc, .enable_reg = MXC_CCM_CCGR3, .enable_shift = MXC_CCM_CCGR3_CG14_OFFSET, @@ -2492,12 +2697,13 @@ static struct clk usboh3_clk[] = { .parent = &tmax2_clk, #if defined(CONFIG_USB_STATIC_IRAM) \ || defined(CONFIG_USB_STATIC_IRAM_PPH) - .secondary = &emi_intr_clk, + .secondary = &emi_intr_clk[0], #else .secondary = &emi_fast_clk, #endif }, }; + static struct clk usb_ahb_clk = { .name = "usb_ahb_clk", .parent = &ipg_clk, @@ -2539,8 +2745,10 @@ static int _clk_usb_phy_set_parent(struct clk *clk, struct clk *parent) return 0; } -static struct clk usb_phy_clk = { +static struct clk usb_phy_clk[] = { + { .name = "usb_phy_clk", + .id = 0, .parent = &pll3_sw_clk, .secondary = &tmax3_clk, .set_parent = _clk_usb_phy_set_parent, @@ -2549,6 +2757,19 @@ static struct clk usb_phy_clk = { .enable_reg = MXC_CCM_CCGR2, .enable_shift = MXC_CCM_CCGR2_CG0_OFFSET, .disable = _clk_disable, + }, + { + .name = "usb_phy_clk", + .id = 1, + .parent = &pll3_sw_clk, + .secondary = &tmax3_clk, + .set_parent = _clk_usb_phy_set_parent, + .recalc = _clk_usb_phy_recalc, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR4, + .enable_shift = MXC_CCM_CCGR4_CG6_OFFSET, + .disable = _clk_disable, + } }; static struct clk esdhc_dep_clks = { @@ -2557,16 +2778,15 @@ static struct clk esdhc_dep_clks = { .secondary = &emi_fast_clk, }; - static void _clk_esdhc1_recalc(struct clk *clk) { u32 reg, prediv, podf; reg = __raw_readl(MXC_CCM_CSCDR1); - prediv = ((reg & MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK) >> - MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET) + 1; - podf = ((reg & MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK) >> - MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET) + 1; + prediv = ((reg & MXC_CCM_CSCDR1_ESDHC1_MSHC2_CLK_PRED_MASK) >> + MXC_CCM_CSCDR1_ESDHC1_MSHC2_CLK_PRED_OFFSET) + 1; + podf = ((reg & MXC_CCM_CSCDR1_ESDHC1_MSHC2_CLK_PODF_MASK) >> + MXC_CCM_CSCDR1_ESDHC1_MSHC2_CLK_PODF_OFFSET) + 1; clk->rate = clk->parent->rate / (prediv * podf); } @@ -2578,20 +2798,49 @@ static int _clk_esdhc1_set_parent(struct clk *clk, struct clk *parent) mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, &lp_apm_clk); reg = __raw_readl(MXC_CCM_CSCMR1) & - ~MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK; - reg |= mux << MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET; + ~MXC_CCM_CSCMR1_ESDHC1_MSHC2_CLK_SEL_MASK; + reg |= mux << MXC_CCM_CSCMR1_ESDHC1_MSHC2_CLK_SEL_OFFSET; __raw_writel(reg, MXC_CCM_CSCMR1); return 0; } + +static int _clk_sdhc1_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg; + u32 div; + u32 pre, post; + + if (cpu_is_mx53()) { + div = clk->parent->rate / rate; + + if ((clk->parent->rate / div) != rate) + return -EINVAL; + + __calc_pre_post_dividers(div, &pre, &post); + + /* Set sdhc1 clock divider */ + reg = __raw_readl(MXC_CCM_CSCDR1) & + ~(MXC_CCM_CSCDR1_ESDHC1_MSHC2_CLK_PRED_MASK | + MXC_CCM_CSCDR1_ESDHC1_MSHC2_CLK_PODF_MASK); + reg |= (post - 1) << MXC_CCM_CSCDR1_ESDHC1_MSHC2_CLK_PODF_OFFSET; + reg |= (pre - 1) << MXC_CCM_CSCDR1_ESDHC1_MSHC2_CLK_PRED_OFFSET; + __raw_writel(reg, MXC_CCM_CSCDR1); + + clk->rate = rate; + } + return 0; +} + static struct clk esdhc1_clk[] = { { .name = "esdhc_clk", .id = 0, - .parent = &pll3_sw_clk, + .parent = &pll2_sw_clk, .set_parent = _clk_esdhc1_set_parent, .recalc = _clk_esdhc1_recalc, + .set_rate = _clk_sdhc1_set_rate, .enable = _clk_enable, .enable_reg = MXC_CCM_CCGR3, .enable_shift = MXC_CCM_CCGR3_CG1_OFFSET, @@ -2621,26 +2870,39 @@ static void _clk_esdhc2_recalc(struct clk *clk) { u32 reg, prediv, podf; - reg = __raw_readl(MXC_CCM_CSCDR1); - prediv = ((reg & MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK) >> - MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET) + 1; - podf = ((reg & MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK) >> - MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET) + 1; + if (cpu_is_mx51()) { + reg = __raw_readl(MXC_CCM_CSCDR1); + prediv = ((reg & MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK) >> + MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET) + 1; + podf = ((reg & MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK) >> + MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET) + 1; - clk->rate = clk->parent->rate / (prediv * podf); + clk->rate = clk->parent->rate / (prediv * podf); + } } static int _clk_esdhc2_set_parent(struct clk *clk, struct clk *parent) { u32 reg, mux; - mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, - &lp_apm_clk); - reg = __raw_readl(MXC_CCM_CSCMR1) & - ~MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK; - reg |= mux << MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET; - __raw_writel(reg, MXC_CCM_CSCMR1); + if (cpu_is_mx51()) { + mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, + &lp_apm_clk); + reg = __raw_readl(MXC_CCM_CSCMR1) & + ~MXC_CCM_CSCMR1_ESDHC3_MSHC2_CLK_SEL_MASK; + reg |= mux << MXC_CCM_CSCMR1_ESDHC3_MSHC2_CLK_SEL_OFFSET; + } else { /* MX53 */ + reg = __raw_readl(MXC_CCM_CSCMR1); + if (parent == &esdhc1_clk[0]) + reg &= ~MXC_CCM_CSCMR1_ESDHC2_CLK_SEL; + else if (parent == &esdhc3_clk[0]) + reg |= MXC_CCM_CSCMR1_ESDHC2_CLK_SEL; + else + BUG(); + + } + __raw_writel(reg, MXC_CCM_CSCMR1); return 0; } @@ -2650,7 +2912,6 @@ static struct clk esdhc2_clk[] = { .id = 1, .parent = &pll3_sw_clk, .set_parent = _clk_esdhc2_set_parent, - .recalc = _clk_esdhc2_recalc, .enable = _clk_enable, .enable_reg = MXC_CCM_CCGR3, .enable_shift = MXC_CCM_CCGR3_CG3_OFFSET, @@ -2677,21 +2938,70 @@ static struct clk esdhc2_clk[] = { static int _clk_esdhc3_set_parent(struct clk *clk, struct clk *parent) { - u32 reg; + u32 reg, mux; - reg = __raw_readl(MXC_CCM_CSCMR1); - if (parent == &esdhc1_clk[0]) - reg &= ~MXC_CCM_CSCMR1_ESDHC3_CLK_SEL; - else if (parent == &esdhc2_clk[0]) - reg |= MXC_CCM_CSCMR1_ESDHC3_CLK_SEL; - else - BUG(); + if (cpu_is_mx51()) { + reg = __raw_readl(MXC_CCM_CSCMR1); + if (parent == &esdhc1_clk[0]) + reg &= ~MXC_CCM_CSCMR1_ESDHC3_CLK_SEL_MX51; + else if (parent == &esdhc2_clk[0]) + reg |= MXC_CCM_CSCMR1_ESDHC3_CLK_SEL_MX51; + else + BUG(); + } else { /* MX53 */ + mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, + &lp_apm_clk); + reg = __raw_readl(MXC_CCM_CSCMR1) & + ~MXC_CCM_CSCMR1_ESDHC3_MSHC2_CLK_SEL_MASK; + reg |= mux << MXC_CCM_CSCMR1_ESDHC3_MSHC2_CLK_SEL_OFFSET; + } __raw_writel(reg, MXC_CCM_CSCMR1); return 0; } +static void _clk_esdhc3_recalc(struct clk *clk) +{ + u32 reg, prediv, podf; + + reg = __raw_readl(MXC_CCM_CSCDR1); + prediv = ((reg & MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PRED_MASK) >> + MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PRED_OFFSET) + 1; + podf = ((reg & MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PODF_MASK) >> + MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PODF_OFFSET) + 1; + + clk->rate = clk->parent->rate / (prediv * podf); +} + +static int _clk_sdhc3_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg; + u32 div; + u32 pre, post; + + if (cpu_is_mx53()) { + div = clk->parent->rate / rate; + + if ((clk->parent->rate / div) != rate) + return -EINVAL; + + __calc_pre_post_dividers(div, &pre, &post); + + /* Set sdhc1 clock divider */ + reg = __raw_readl(MXC_CCM_CSCDR1) & + ~(MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PRED_MASK | + MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PODF_MASK); + reg |= (post - 1) << MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PODF_OFFSET; + reg |= (pre - 1) << MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PRED_OFFSET; + __raw_writel(reg, MXC_CCM_CSCDR1); + + clk->rate = rate; + } + return 0; +} + + static struct clk esdhc3_clk[] = { { .name = "esdhc_clk", @@ -2722,18 +3032,26 @@ static struct clk esdhc3_clk[] = { }, }; - static int _clk_esdhc4_set_parent(struct clk *clk, struct clk *parent) { u32 reg; - - reg = __raw_readl(MXC_CCM_CSCMR1); - if (parent == &esdhc1_clk[0]) - reg &= ~MXC_CCM_CSCMR1_ESDHC4_CLK_SEL; - else if (parent == &esdhc2_clk[0]) - reg |= MXC_CCM_CSCMR1_ESDHC4_CLK_SEL; - else - BUG(); + if (cpu_is_mx51()) { + reg = __raw_readl(MXC_CCM_CSCMR1); + if (parent == &esdhc1_clk[0]) + reg &= ~MXC_CCM_CSCMR1_ESDHC4_CLK_SEL; + else if (parent == &esdhc2_clk[0]) + reg |= MXC_CCM_CSCMR1_ESDHC4_CLK_SEL; + else + BUG(); + } else {/*MX53 */ + reg = __raw_readl(MXC_CCM_CSCMR1); + if (parent == &esdhc1_clk[0]) + reg &= ~MXC_CCM_CSCMR1_ESDHC4_CLK_SEL; + else if (parent == &esdhc3_clk[0]) + reg |= MXC_CCM_CSCMR1_ESDHC4_CLK_SEL; + else + BUG(); + } __raw_writel(reg, MXC_CCM_CSCMR1); @@ -2770,6 +3088,73 @@ static struct clk esdhc4_clk[] = { }, }; +static struct clk sata_clk = { + .name = "sata_clk", + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR4, + .enable_shift = MXC_CCM_CCGR4_CG1_OFFSET, + .disable = _clk_disable, +}; + +static struct clk ieee_1588_clk = { + .name = "ieee_1588_clk", + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR7, + .enable_shift = MXC_CCM_CCGR7_CG3_OFFSET, + .disable = _clk_disable, +}; + +static struct clk mlb_clk = { + .name = "mlb_clk", + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR7, + .enable_shift = MXC_CCM_CCGR7_CG2_OFFSET, + .disable = _clk_disable, +}; + +static struct clk can1_clk[] = { + { + .name = "can1_clk", + .parent = &pll3_sw_clk, + .secondary = &can1_clk[1], + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR6, + .enable_shift = MXC_CCM_CCGR6_CG11_OFFSET, + .disable = _clk_disable, + }, + { + .name = "can1_ipg_clk", + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR6, + .enable_shift = MXC_CCM_CCGR6_CG10_OFFSET, + .disable = _clk_disable, + }, +}; + +static struct clk can2_clk[] = { + { + .name = "can2_clk", + .parent = &pll3_sw_clk, + .secondary = &can2_clk[1], + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR4, + .enable_shift = MXC_CCM_CCGR4_CG4_OFFSET, + .disable = _clk_disable, + }, + { + .name = "can2_ipg_clk", + .parent = &ipg_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR4, + .enable_shift = MXC_CCM_CCGR4_CG3_OFFSET, + .disable = _clk_disable, + }, +}; + static int _clk_sim_set_parent(struct clk *clk, struct clk *parent) { u32 reg, mux; @@ -3104,30 +3489,39 @@ static int _clk_ddr_set_parent(struct clk *clk, struct clk *parent) reg = __raw_readl(MXC_CCM_CBCMR); reg2 = __raw_readl(MXC_CCM_CBCDR); - mux = _get_mux_ddr(parent, &axi_a_clk, &axi_b_clk, &emi_slow_clk, &ahb_clk, &ddr_hf_clk); + if (cpu_is_mx51()) { + clk->parent = &ddr_hf_clk; + mux = _get_mux_ddr(parent, &axi_a_clk, &axi_b_clk, &emi_slow_clk, &ahb_clk, &ddr_hf_clk); + } else { + clk->parent = &axi_a_clk; + mux = _get_mux_ddr(parent, &axi_a_clk, &axi_b_clk, &emi_slow_clk, &ahb_clk, NULL); + } if (mux < 4) { reg = (reg & ~MXC_CCM_CBCMR_DDR_CLK_SEL_MASK) | (mux << MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET); __raw_writel(reg, MXC_CCM_CBCMR); - reg2 = (reg2 & ~MXC_CCM_CBCDR_DDR_HF_SEL); + if (cpu_is_mx51()) + reg2 = (reg2 & ~MXC_CCM_CBCDR_DDR_HF_SEL); } else { reg2 = (reg2 & ~MXC_CCM_CBCDR_DDR_HF_SEL) | (MXC_CCM_CBCDR_DDR_HF_SEL); } - __raw_writel(reg2, MXC_CCM_CBCDR); - getnstimeofday(&nstimeofday); - while (__raw_readl(MXC_CCM_CDHIPR) & - MXC_CCM_CDHIPR_DDR_HF_CLK_SEL_BUSY){ - getnstimeofday(&curtime); - if ((curtime.tv_nsec - nstimeofday.tv_nsec) > SPIN_DELAY) - panic("_clk_ddr_set_parent failed\n"); + if (cpu_is_mx51()) { + __raw_writel(reg2, MXC_CCM_CBCDR); + getnstimeofday(&nstimeofday); + while (__raw_readl(MXC_CCM_CDHIPR) & + MXC_CCM_CDHIPR_DDR_HF_CLK_SEL_BUSY){ + getnstimeofday(&curtime); + if ((curtime.tv_nsec - nstimeofday.tv_nsec) > SPIN_DELAY) + panic("_clk_ddr_set_parent failed\n"); + } } return 0; } static struct clk ddr_clk = { .name = "ddr_clk", - .parent = &ddr_hf_clk, + .parent = &axi_b_clk, .set_parent = _clk_ddr_set_parent, .flags = RATE_PROPAGATES, }; @@ -3172,7 +3566,7 @@ static int _clk_vpu_enable(struct clk *clk) if (cpu_is_mx51_rev(CHIP_REV_2_0) < 0) { clk_set_parent(&vpu_clk[0], &ahb_clk); clk_set_parent(&vpu_clk[1], &ahb_clk); - } else { + } else if (cpu_is_mx51()) { clk_set_parent(&vpu_clk[0], &axi_a_clk); clk_set_parent(&vpu_clk[1], &axi_a_clk); } @@ -3186,8 +3580,10 @@ static void _clk_vpu_disable(struct clk *clk) _clk_disable(clk); /* Set VPU's parent to be axi_b when its disabled. */ - clk_set_parent(&vpu_clk[0], &axi_b_clk); - clk_set_parent(&vpu_clk[1], &axi_b_clk); + if (cpu_is_mx51()) { + clk_set_parent(&vpu_clk[0], &axi_b_clk); + clk_set_parent(&vpu_clk[1], &axi_b_clk); + } } static struct clk vpu_clk[] = { @@ -3214,7 +3610,7 @@ static struct clk vpu_clk[] = { .name = "vpu_emi_clk", .parent = &emi_fast_clk, #ifdef CONFIG_MXC_VPU_IRAM - .secondary = &emi_intr_clk, + .secondary = &emi_intr_clk[0], #endif } }; @@ -3223,7 +3619,7 @@ static int _clk_lpsr_set_parent(struct clk *clk, struct clk *parent) { u32 reg, mux; reg = __raw_readl(MXC_CCM_CLPCR); - mux = _get_mux(parent, &ckil_clk, &fpm_clk, &fpm_div2_clk, NULL); + mux = _get_mux(parent, &ckil_clk, &osc_clk, NULL, NULL); reg = (reg & ~MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK) | (mux << MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET); __raw_writel(reg, MXC_CCM_CLPCR); @@ -3424,13 +3820,111 @@ static struct clk gpu2d_clk = { .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE, }; +static void cko1_recalc(struct clk *clk) +{ + unsigned long rate; + u32 reg; + + reg = __raw_readl(MXC_CCM_CCOSR); + reg &= MXC_CCM_CCOSR_CKOL_DIV_MASK; + reg = reg >> MXC_CCM_CCOSR_CKOL_DIV_OFFSET; + rate = clk->parent->rate; + clk->rate = rate / (reg + 1); +} + +static int cko1_enable(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_CCOSR); + reg |= MXC_CCM_CCOSR_CKOL_EN; + __raw_writel(reg, MXC_CCM_CCOSR); + return 0; +} + +static void cko1_disable(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_CCOSR); + reg &= ~MXC_CCM_CCOSR_CKOL_EN; + __raw_writel(reg, MXC_CCM_CCOSR); +} + +static int cko1_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg, div; + + div = (clk->parent->rate/rate - 1) & 0x7; + reg = __raw_readl(MXC_CCM_CCOSR); + reg &= ~MXC_CCM_CCOSR_CKOL_DIV_MASK; + reg |= div << MXC_CCM_CCOSR_CKOL_DIV_OFFSET; + __raw_writel(reg, MXC_CCM_CCOSR); + return 0; +} + +static unsigned long cko1_round_rate(struct clk *clk, unsigned long rate) +{ + u32 div; + + div = clk->parent->rate / rate; + div = div < 1 ? 1 : div; + div = div > 8 ? 8 : div; + return clk->parent->rate / div; +} + +static int cko1_set_parent(struct clk *clk, struct clk *parent) +{ + u32 sel, reg; + + if (parent == &cpu_clk) + sel = 0; + else if (parent == &pll1_sw_clk) + sel = 1; + else if (parent == &pll2_sw_clk) + sel = 2; + else if (parent == &pll3_sw_clk) + sel = 3; + else if (parent == &emi_slow_clk) + sel = 4; + else if (parent == &pll4_sw_clk) + sel = 5; + else if (parent == &emi_enfc_clk) + sel = 6; + else if (parent == &ipu_di_clk[0]) + sel = 8; + else if (parent == &ahb_clk) + sel = 11; + else if (parent == &ipg_clk) + sel = 12; + else if (parent == &ipg_perclk) + sel = 13; + else if (parent == &ckil_clk) + sel = 14; + else + return -EINVAL; + + reg = __raw_readl(MXC_CCM_CCOSR); + reg &= ~MXC_CCM_CCOSR_CKOL_SEL_MASK; + reg |= sel << MXC_CCM_CCOSR_CKOL_SEL_OFFSET; + __raw_writel(reg, MXC_CCM_CCOSR); + return 0; +} +static struct clk cko1_clk = { + .name = "cko1_clk", + .recalc = cko1_recalc, + .enable = cko1_enable, + .disable = cko1_disable, + .set_rate = cko1_set_rate, + .round_rate = cko1_round_rate, + .set_parent = cko1_set_parent, +}; + static struct clk *mxc_clks[] = { &osc_clk, &ckih_clk, &ckih2_clk, &ckil_clk, - &fpm_clk, - &fpm_div2_clk, &pll1_main_clk, &pll1_sw_clk, &pll2_sw_clk, @@ -3471,8 +3965,6 @@ static struct clk *mxc_clks[] = { &spba_clk, &i2c_clk[0], &i2c_clk[1], - &hsi2c_clk, - &hsi2c_serial_clk, &gpt_clk[0], &gpt_clk[1], &gpt_clk[2], @@ -3505,7 +3997,7 @@ static struct clk *mxc_clks[] = { &usboh3_clk[0], &usboh3_clk[1], &usb_ahb_clk, - &usb_phy_clk, + &usb_phy_clk[0], &usb_utmi_clk, &usb_clk, &esdhc1_clk[0], @@ -3517,18 +4009,14 @@ static struct clk *mxc_clks[] = { &esdhc4_clk[0], &esdhc4_clk[1], &esdhc_dep_clks, - &sim_clk[0], - &sim_clk[1], &emi_slow_clk, &ddr_clk, &emi_enfc_clk, &emi_fast_clk, - &emi_intr_clk, + &emi_intr_clk[0], &spdif_xtal_clk, &spdif0_clk[0], &spdif0_clk[1], - &spdif1_clk[0], - &spdif1_clk[1], &arm_axi_clk, &vpu_clk[0], &vpu_clk[1], @@ -3541,24 +4029,19 @@ static struct clk *mxc_clks[] = { &fec_clk[0], &fec_clk[1], &fec_clk[2], - &mipi_hsc1_clk, - &mipi_hsc2_clk, - &mipi_esc_clk, - &mipi_hsp_clk, &sahara_clk[0], &sahara_clk[1], &gpu3d_clk, &garb_clk, - &emi_garb_clk, - &ddr_hf_clk, &gpu2d_clk, &scc_clk[0], &scc_clk[1], + &cko1_clk, }; static void clk_tree_init(void) { - u32 reg, reg2, dp_ctl; + u32 reg, dp_ctl; ipg_perclk.set_parent(&ipg_perclk, &lp_apm_clk); @@ -3575,19 +4058,32 @@ static void clk_tree_init(void) /* set pll1_main_clk parent */ pll1_main_clk.parent = &osc_clk; - dp_ctl = __raw_readl(pll1_base + MXC_PLL_DP_CTL); - if ((dp_ctl & MXC_PLL_DP_CTL_REF_CLK_SEL_MASK) == 0) - pll1_main_clk.parent = &fpm_clk; + /* set pll2_sw_clk parent */ pll2_sw_clk.parent = &osc_clk; - dp_ctl = __raw_readl(pll2_base + MXC_PLL_DP_CTL); - if ((dp_ctl & MXC_PLL_DP_CTL_REF_CLK_SEL_MASK) == 0) - pll2_sw_clk.parent = &fpm_clk; + /* set pll3_clk parent */ pll3_sw_clk.parent = &osc_clk; - dp_ctl = __raw_readl(pll3_base + MXC_PLL_DP_CTL); - if ((dp_ctl & MXC_PLL_DP_CTL_REF_CLK_SEL_MASK) == 0) - pll3_sw_clk.parent = &fpm_clk; + + if (cpu_is_mx51()) { + dp_ctl = __raw_readl(pll1_base + MXC_PLL_DP_CTL); + if ((dp_ctl & MXC_PLL_DP_CTL_REF_CLK_SEL_MASK) == 0) + pll1_main_clk.parent = &fpm_clk; + + dp_ctl = __raw_readl(pll2_base + MXC_PLL_DP_CTL); + if ((dp_ctl & MXC_PLL_DP_CTL_REF_CLK_SEL_MASK) == 0) + pll2_sw_clk.parent = &fpm_clk; + + dp_ctl = __raw_readl(pll3_base + MXC_PLL_DP_CTL); + if ((dp_ctl & MXC_PLL_DP_CTL_REF_CLK_SEL_MASK) == 0) + pll3_sw_clk.parent = &fpm_clk; + } else { + /* set pll4_clk parent */ + pll4_sw_clk.parent = &osc_clk; + } + + if (cpu_is_mx53()) + tve_clk.parent = &pll4_sw_clk; /* set emi_slow_clk parent */ emi_slow_clk.parent = &main_bus_clk; @@ -3604,32 +4100,13 @@ static void clk_tree_init(void) if ((reg & MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL) == 0) ipg_perclk.parent = &main_bus_clk; } - - /* set DDR clock parent */ - reg = __raw_readl(MXC_CCM_CBCMR) & MXC_CCM_CBCMR_DDR_CLK_SEL_MASK; - reg >>= MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET; - reg2 = __raw_readl(MXC_CCM_CBCDR) & MXC_CCM_CBCDR_DDR_HF_SEL; - reg2 >>= MXC_CCM_CBCDR_DDR_HF_SEL_OFFSET; - - if (reg2) { - ddr_clk.parent = &ddr_hf_clk; - } else { - if (reg == 0) { - ddr_clk.parent = &axi_a_clk; - } else if (reg == 1) { - ddr_clk.parent = &axi_b_clk; - } else if (reg == 2) { - ddr_clk.parent = &emi_slow_clk; - } else { - ddr_clk.parent = &ahb_clk; - } - } } + int __init mx51_clocks_init(unsigned long ckil, unsigned long osc, unsigned long ckih1, unsigned long ckih2) { __iomem void *base; - struct clk **clkp; + struct clk **clkp, *tclk; int i = 0, j = 0, reg; int wp_cnt = 0; @@ -3680,18 +4157,62 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc, unsigned long ckih_clk.rate = ckih1; ckih2_clk.rate = ckih2; + /* Fix up clocks unique to MX51. */ + esdhc2_clk[0].recalc = _clk_esdhc2_recalc; + clk_tree_init(); for (clkp = mxc_clks; clkp < mxc_clks + ARRAY_SIZE(mxc_clks); clkp++) clk_register(*clkp); + clk_register(&fpm_clk); + clk_register(&fpm_div2_clk); + clk_register(&hsi2c_clk); + clk_register(&hsi2c_serial_clk); + clk_register(&sim_clk[0]); + clk_register(&sim_clk[1]); + clk_register(&mipi_hsc1_clk); + clk_register(&mipi_hsc2_clk); + clk_register(&mipi_esc_clk); + clk_register(&mipi_hsp_clk); + clk_register(&spdif1_clk[0]); + clk_register(&spdif1_clk[1]); + clk_register(&ddr_hf_clk); + clk_register(&emi_garb_clk); + + /* set DDR clock parent */ + reg = 0; + if (cpu_is_mx51_rev(CHIP_REV_2_0) >= 1) { + reg = __raw_readl(MXC_CCM_CBCDR) & MXC_CCM_CBCDR_DDR_HF_SEL; + reg >>= MXC_CCM_CBCDR_DDR_HF_SEL_OFFSET; + + if (reg) + tclk = &ddr_hf_clk; + } + if (reg == 0) { + reg = __raw_readl(MXC_CCM_CBCMR) & + MXC_CCM_CBCMR_DDR_CLK_SEL_MASK; + reg >>= MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET; + + if (reg == 0) { + tclk = &axi_a_clk; + } else if (reg == 1) { + tclk = &axi_b_clk; + } else if (reg == 2) { + tclk = &emi_slow_clk; + } else { + tclk = &ahb_clk; + } + } + clk_set_parent(&ddr_clk, tclk); + /*Setup the LPM bypass bits */ reg = __raw_readl(MXC_CCM_CLPCR); reg |= MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS | MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS | MXC_CCM_CLPCR_BYPASS_RTIC_LPM_HS - | MXC_CCM_CLPCR_BYPASS_SCC_LPM_HS - | MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS; + | MXC_CCM_CLPCR_BYPASS_SCC_LPM_HS_MX51 + | MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS_MX51; __raw_writel(reg, MXC_CCM_CLPCR); /* Disable the handshake with HSC block as its not @@ -3710,13 +4231,7 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc, unsigned long propagate_rate(&pll2_sw_clk); clk_enable(&cpu_clk); - reg = __raw_readl(MXC_CCM_CBCDR) & MXC_CCM_CBCDR_DDR_HF_SEL; - reg >>= MXC_CCM_CBCDR_DDR_HF_SEL_OFFSET; - if (reg) - clk_set_parent(&ddr_clk, &ddr_hf_clk); - else - clk_set_parent(&ddr_clk, &axi_a_clk); /* Initialise the parents to be axi_b, parents are set to * axi_a when the clocks are enabled. @@ -3768,7 +4283,7 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc, unsigned long clk_set_parent(&ssi_ext2_clk, &ssi2_clk[0]); /* move usb_phy_clk to 24MHz */ - clk_set_parent(&usb_phy_clk, &osc_clk); + clk_set_parent(&usb_phy_clk[0], &osc_clk); /* set usboh3_clk to pll2 */ clk_set_parent(&usboh3_clk[0], &pll2_sw_clk); @@ -3895,6 +4410,308 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc, unsigned long return 0; } +int __init mx53_clocks_init(unsigned long ckil, unsigned long osc, unsigned long ckih1, unsigned long ckih2) +{ + __iomem void *base; + struct clk **clkp, *tclk; + int i = 0, j = 0, reg; + int wp_cnt = 0; + + pll1_base = ioremap(MX53_BASE_ADDR(PLL1_BASE_ADDR), SZ_4K); + pll2_base = ioremap(MX53_BASE_ADDR(PLL2_BASE_ADDR), SZ_4K); + pll3_base = ioremap(MX53_BASE_ADDR(PLL3_BASE_ADDR), SZ_4K); + pll4_base = ioremap(MX53_BASE_ADDR(PLL4_BASE_ADDR), SZ_4K); + + /* Turn off all possible clocks */ + if (mxc_jtag_enabled) { + __raw_writel(1 << MXC_CCM_CCGR0_CG0_OFFSET | + 1 << MXC_CCM_CCGR0_CG1_OFFSET | + 1 << MXC_CCM_CCGR0_CG2_OFFSET | + 3 << MXC_CCM_CCGR0_CG3_OFFSET | + 3 << MXC_CCM_CCGR0_CG4_OFFSET | + 3 << MXC_CCM_CCGR0_CG8_OFFSET | + 3 << MXC_CCM_CCGR0_CG9_OFFSET | + 1 << MXC_CCM_CCGR0_CG12_OFFSET | + 1 << MXC_CCM_CCGR0_CG13_OFFSET | + 1 << MXC_CCM_CCGR0_CG14_OFFSET, MXC_CCM_CCGR0); + } else { + __raw_writel(1 << MXC_CCM_CCGR0_CG0_OFFSET | + 1 << MXC_CCM_CCGR0_CG1_OFFSET | + 3 << MXC_CCM_CCGR0_CG3_OFFSET | + 3 << MXC_CCM_CCGR0_CG8_OFFSET | + 3 << MXC_CCM_CCGR0_CG9_OFFSET | + 1 << MXC_CCM_CCGR0_CG12_OFFSET | + 1 << MXC_CCM_CCGR0_CG13_OFFSET | + 3 << MXC_CCM_CCGR0_CG14_OFFSET, MXC_CCM_CCGR0); + } + + __raw_writel(0, MXC_CCM_CCGR1); + __raw_writel(0, MXC_CCM_CCGR2); + __raw_writel(0, MXC_CCM_CCGR3); + __raw_writel(1 << MXC_CCM_CCGR4_CG8_OFFSET, MXC_CCM_CCGR4); + + __raw_writel(1 << MXC_CCM_CCGR5_CG2_OFFSET | + 1 << MXC_CCM_CCGR5_CG6_OFFSET | + 3 << MXC_CCM_CCGR5_CG7_OFFSET | + 1 << MXC_CCM_CCGR5_CG8_OFFSET | + 3 << MXC_CCM_CCGR5_CG9_OFFSET | + 1 << MXC_CCM_CCGR5_CG10_OFFSET | + 3 << MXC_CCM_CCGR5_CG11_OFFSET, MXC_CCM_CCGR5); + + __raw_writel(3 << MXC_CCM_CCGR6_CG0_OFFSET | + 3 << MXC_CCM_CCGR6_CG1_OFFSET | + 3 << MXC_CCM_CCGR6_CG4_OFFSET | + 3 << MXC_CCM_CCGR6_CG8_OFFSET | + 3 << MXC_CCM_CCGR6_CG9_OFFSET | + 3 << MXC_CCM_CCGR6_CG12_OFFSET | + 3 << MXC_CCM_CCGR6_CG13_OFFSET , MXC_CCM_CCGR6); + + __raw_writel(0, MXC_CCM_CCGR7); + + ckil_clk.rate = ckil; + osc_clk.rate = osc; + ckih_clk.rate = ckih1; + ckih2_clk.rate = ckih2; + + usb_phy_clk[0].enable_reg = MXC_CCM_CCGR4; + usb_phy_clk[0].enable_shift = MXC_CCM_CCGR4_CG5_OFFSET; + + ipumux1_clk.enable_reg = MXC_CCM_CCGR5; + ipumux1_clk.enable_shift = MXC_CCM_CCGR5_CG6_OFFSET; + ipumux2_clk.enable_reg = MXC_CCM_CCGR6; + ipumux2_clk.enable_shift = MXC_CCM_CCGR6_CG0_OFFSET; + + esdhc3_clk[0].recalc = _clk_esdhc3_recalc; + esdhc3_clk[0].set_rate = _clk_sdhc3_set_rate; + +#ifdef CONFIG_MXC_VPU_IRAM + vpu_clk[2].secondary = &emi_intr_clk[1]; +#endif +#if defined(CONFIG_USB_STATIC_IRAM) \ + || defined(CONFIG_USB_STATIC_IRAM_PPH) + usboh3_clk[1].secondary = &emi_intr_clk[1]; +#endif +#ifdef CONFIG_SND_MXC_SOC_IRAM + ssi2_clk[2].secondary = &emi_intr_clk[1]; + ssi1_clk[2].secondary = &emi_intr_clk[1]; +#endif +#ifdef CONFIG_SDMA_IRAM + sdma_clk[1].secondary = &emi_intr_clk[1]; +#endif + + clk_tree_init(); + + for (clkp = mxc_clks; clkp < mxc_clks + ARRAY_SIZE(mxc_clks); clkp++) + clk_register(*clkp); + + clk_register(&pll4_sw_clk); + clk_register(&emi_intr_clk[1]); + clk_register(&uart4_clk[0]); + clk_register(&uart4_clk[1]); + clk_register(&uart5_clk[0]); + clk_register(&uart5_clk[1]); + clk_register(&i2c_clk[2]); + clk_register(&usb_phy_clk[1]); + clk_register(&ocram_clk); + clk_register(&sata_clk); + clk_register(&ieee_1588_clk); + clk_register(&mlb_clk); + + /* set DDR clock parent */ + reg = __raw_readl(MXC_CCM_CBCMR) & + MXC_CCM_CBCMR_DDR_CLK_SEL_MASK; + reg >>= MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET; + if (reg == 0) { + tclk = &axi_a_clk; + } else if (reg == 1) { + tclk = &axi_b_clk; + } else if (reg == 2) { + tclk = &emi_slow_clk; + } else { + tclk = &ahb_clk; + } + clk_set_parent(&ddr_clk, tclk); + + clk_set_parent(&esdhc1_clk[2], &tmax2_clk); + clk_set_parent(&esdhc2_clk[0], &esdhc1_clk[0]); + clk_set_parent(&esdhc3_clk[0], &pll2_sw_clk); + +#if 0 + /*Setup the LPM bypass bits */ + reg = __raw_readl(MXC_CCM_CLPCR); + reg |= MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS + | MXC_CCM_CLPCR_BYPASS_RTIC_LPM_HS + | MXC_CCM_CLPCR_BYPASS_SCC_LPM_HS + | MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS; + __raw_writel(reg, MXC_CCM_CLPCR); +#endif + + /* Disable the handshake with HSC block as its not + * initialised right now. + */ + reg = __raw_readl(MXC_CCM_CCDR); + reg |= MXC_CCM_CCDR_EMI_HS_MASK; + __raw_writel(reg, MXC_CCM_CCDR); + + /* This will propagate to all children and init all the clock rates */ + propagate_rate(&osc_clk); + propagate_rate(&ckih_clk); + propagate_rate(&ckih2_clk); + propagate_rate(&ckil_clk); + propagate_rate(&pll1_sw_clk); + propagate_rate(&pll2_sw_clk); + propagate_rate(&pll3_sw_clk); + + clk_enable(&cpu_clk); + + clk_enable(&main_bus_clk); + + /* Initialise the parents to be axi_b, parents are set to + * axi_a when the clocks are enabled. + */ + + clk_set_parent(&vpu_clk[0], &axi_b_clk); + clk_set_parent(&vpu_clk[1], &axi_b_clk); + clk_set_parent(&gpu3d_clk, &axi_a_clk); + clk_set_parent(&gpu2d_clk, &axi_a_clk); + + /* move cspi to 24MHz */ + clk_set_parent(&cspi_main_clk, &lp_apm_clk); + clk_set_rate(&cspi_main_clk, 12000000); + /*move the spdif0 to spdif_xtal_ckl */ + clk_set_parent(&spdif0_clk[0], &spdif_xtal_clk); + /*set the SPDIF dividers to 1 */ + reg = __raw_readl(MXC_CCM_CDCDR); + reg &= ~MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK; + reg &= ~MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK; + __raw_writel(reg, MXC_CCM_CDCDR); + + /* Move SSI clocks to SSI_LP_APM clock */ + clk_set_parent(&ssi_lp_apm_clk, &lp_apm_clk); + + clk_set_parent(&ssi1_clk[0], &ssi_lp_apm_clk); + /* set the SSI dividers to divide by 2 */ + reg = __raw_readl(MXC_CCM_CS1CDR); + reg &= ~MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK; + reg &= ~MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK; + reg |= 1 << MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET; + __raw_writel(reg, MXC_CCM_CS1CDR); + + clk_set_parent(&ssi2_clk[0], &ssi_lp_apm_clk); + reg = __raw_readl(MXC_CCM_CS2CDR); + reg &= ~MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK; + reg &= ~MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK; + reg |= 1 << MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET; + __raw_writel(reg, MXC_CCM_CS2CDR); + + /* Change the SSI_EXT1_CLK to be sourced from SSI1_CLK_ROOT */ + clk_set_parent(&ssi_ext1_clk, &ssi1_clk[0]); + clk_set_parent(&ssi_ext2_clk, &ssi2_clk[0]); + + /* move usb_phy_clk to 24MHz */ + clk_set_parent(&usb_phy_clk[0], &osc_clk); + clk_set_parent(&usb_phy_clk[1], &osc_clk); + + /* set usboh3_clk to pll2 */ + clk_set_parent(&usboh3_clk[0], &pll2_sw_clk); + reg = __raw_readl(MXC_CCM_CSCDR1); + reg &= ~MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK; + reg &= ~MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK; + reg |= 4 << MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET; + reg |= 1 << MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET; + __raw_writel(reg, MXC_CCM_CSCDR1); + + /* set SDHC root clock as 200MHZ*/ + clk_set_rate(&esdhc1_clk[0], 200000000); + clk_set_rate(&esdhc3_clk[0], 200000000); + + /* Set the current working point. */ + cpu_wp_tbl = get_cpu_wp(&cpu_wp_nr); + /* Update the cpu working point table based on the PLL1 freq + * at boot time + */ + if (pll1_main_clk.rate <= cpu_wp_tbl[cpu_wp_nr - 1].cpu_rate) + wp_cnt = 1; + else if (pll1_main_clk.rate <= cpu_wp_tbl[1].cpu_rate && + pll1_main_clk.rate > cpu_wp_tbl[2].cpu_rate) + wp_cnt = cpu_wp_nr - 1; + else + wp_cnt = cpu_wp_nr; + + cpu_wp_tbl[0].cpu_rate = pll1_main_clk.rate; + + if (wp_cnt == 1) { + cpu_wp_tbl[0] = cpu_wp_tbl[cpu_wp_nr - 1]; + memset(&cpu_wp_tbl[cpu_wp_nr - 1], 0, sizeof(struct cpu_wp)); + memset(&cpu_wp_tbl[cpu_wp_nr - 2], 0, sizeof(struct cpu_wp)); + } else if (wp_cnt < cpu_wp_nr) { + for (i = 0; i < wp_cnt; i++) + cpu_wp_tbl[i] = cpu_wp_tbl[i+1]; + memset(&cpu_wp_tbl[i], 0, sizeof(struct cpu_wp)); + } + + if (wp_cnt < cpu_wp_nr) { + set_num_cpu_wp(wp_cnt); + cpu_wp_tbl = get_cpu_wp(&cpu_wp_nr); + } + + + for (j = 0; j < cpu_wp_nr; j++) { + if ((ddr_clk.parent == &ddr_hf_clk)) { + /* Change the CPU podf divider based on the boot up + * pll1 rate. + */ + cpu_wp_tbl[j].cpu_podf = + (pll1_main_clk.rate / cpu_wp_tbl[j].cpu_rate) + - 1; + if (pll1_main_clk.rate/(cpu_wp_tbl[j].cpu_podf + 1) > + cpu_wp_tbl[j].cpu_rate) { + cpu_wp_tbl[j].cpu_podf++; + cpu_wp_tbl[j].cpu_rate = + pll1_main_clk.rate/ + (1000 * (cpu_wp_tbl[j].cpu_podf + 1)); + cpu_wp_tbl[j].cpu_rate *= 1000; + } + if (pll1_main_clk.rate/(cpu_wp_tbl[j].cpu_podf + 1) < + cpu_wp_tbl[j].cpu_rate) { + cpu_wp_tbl[j].cpu_rate = pll1_main_clk.rate; + } + } + cpu_wp_tbl[j].pll_rate = pll1_main_clk.rate; + } + /* Set the current working point. */ + for (i = 0; i < cpu_wp_nr; i++) { + if (clk_get_rate(&cpu_clk) == cpu_wp_tbl[i].cpu_rate) { + cpu_curr_wp = i; + break; + } + } + if (i > cpu_wp_nr) + BUG(); + + propagate_rate(&osc_clk); + propagate_rate(&pll1_sw_clk); + propagate_rate(&pll2_sw_clk); + propagate_rate(&pll3_sw_clk); + + clk_set_parent(&arm_axi_clk, &axi_b_clk); + clk_set_parent(&ipu_clk[0], &axi_b_clk); + clk_set_parent(&uart_main_clk, &pll3_sw_clk); + clk_set_parent(&gpu3d_clk, &axi_b_clk); + clk_set_parent(&gpu2d_clk, &axi_b_clk); + + clk_set_parent(&emi_slow_clk, &ahb_clk); + clk_set_rate(&emi_slow_clk, clk_round_rate(&emi_slow_clk, 130000000)); + + /* Change the NFC clock rate to be 1:4 ratio with emi clock. */ + clk_set_rate(&emi_enfc_clk, clk_round_rate(&emi_enfc_clk, + (clk_get_rate(&emi_slow_clk))/4)); + + base = ioremap(MX53_BASE_ADDR(GPT1_BASE_ADDR), SZ_4K); + mxc_timer_init(&gpt_clk[0], base, MXC_INT_GPT); + return 0; +} + /*! * Setup cpu clock based on working point. * @param wp cpu freq working point diff --git a/arch/arm/mach-mx5/cpu.c b/arch/arm/mach-mx5/cpu.c index be1c43d62f1e..b487d2d16e10 100644 --- a/arch/arm/mach-mx5/cpu.c +++ b/arch/arm/mach-mx5/cpu.c @@ -26,21 +26,13 @@ #include <linux/iram_alloc.h> #include <linux/io.h> #include <linux/clk.h> +#include <mach/common.h> #include <mach/hardware.h> #include "crm_regs.h" void __iomem *arm_plat_base; void __iomem *gpc_base; -/*! - * CPU initialization. It is called by fixup_mxc_board() - */ -void __init mxc_cpu_init(void) -{ - if (!system_rev) - mxc_set_system_rev(0x51, CHIP_REV_1_0); -} - static void __init mipi_hsc_disable(void) { void __iomem *reg_hsc_mcd = ioremap(MIPI_HSC_BASE_ADDR, SZ_4K); @@ -76,7 +68,7 @@ void mx51_vpu_reset(void) u32 reg; void __iomem *src_base; - src_base = ioremap(SRC_BASE_ADDR, PAGE_SIZE); + src_base = ioremap(MX53_BASE_ADDR(SRC_BASE_ADDR), PAGE_SIZE); /* mask interrupt due to vpu passed reset */ reg = __raw_readl(src_base + 0x18); @@ -98,22 +90,25 @@ static int __init post_cpu_init(void) unsigned int reg; int iram_size = IRAM_SIZE; - mipi_hsc_disable(); + if (cpu_is_mx51()) { + mipi_hsc_disable(); #if defined(CONFIG_MXC_SECURITY_SCC) || defined(CONFIG_MXC_SECURITY_SCC_MODULE) - if (cpu_is_mx51()) iram_size -= SCC_RAM_SIZE; #endif - iram_init(IRAM_BASE_ADDR, iram_size); + iram_init(MX51_IRAM_BASE_ADDR, iram_size); + } else { + iram_init(MX53_IRAM_BASE_ADDR, iram_size); + } - gpc_base = ioremap(GPC_BASE_ADDR, SZ_4K); + gpc_base = ioremap(MX53_BASE_ADDR(GPC_BASE_ADDR), SZ_4K); /* Set ALP bits to 000. Set ALP_EN bit in Arm Memory Controller reg. */ - arm_plat_base = ioremap(ARM_BASE_ADDR, SZ_4K); + arm_plat_base = ioremap(MX53_BASE_ADDR(ARM_BASE_ADDR), SZ_4K); reg = 0x8; __raw_writel(reg, MXC_CORTEXA8_PLAT_AMC); - base = ioremap(AIPS1_BASE_ADDR, SZ_4K); + base = ioremap(MX53_BASE_ADDR(AIPS1_BASE_ADDR), SZ_4K); __raw_writel(0x0, base + 0x40); __raw_writel(0x0, base + 0x44); __raw_writel(0x0, base + 0x48); @@ -122,7 +117,7 @@ static int __init post_cpu_init(void) __raw_writel(reg, base + 0x50); iounmap(base); - base = ioremap(AIPS2_BASE_ADDR, SZ_4K); + base = ioremap(MX53_BASE_ADDR(AIPS2_BASE_ADDR), SZ_4K); __raw_writel(0x0, base + 0x40); __raw_writel(0x0, base + 0x44); __raw_writel(0x0, base + 0x48); @@ -134,7 +129,7 @@ static int __init post_cpu_init(void) /*Allow for automatic gating of the EMI internal clock. * If this is done, emi_intr CCGR bits should be set to 11. */ - base = ioremap(M4IF_BASE_ADDR, SZ_4K); + base = ioremap(MX53_BASE_ADDR(M4IF_BASE_ADDR), SZ_4K); reg = __raw_readl(base + 0x8c); reg &= ~0x1; __raw_writel(reg, base + 0x8c); diff --git a/arch/arm/mach-mx5/crm_regs.h b/arch/arm/mach-mx5/crm_regs.h index 32b2addbf3b9..e53f55d258eb 100644 --- a/arch/arm/mach-mx5/crm_regs.h +++ b/arch/arm/mach-mx5/crm_regs.h @@ -17,11 +17,13 @@ extern void __iomem *ccm_base; extern void __iomem *pll1_base; extern void __iomem *pll2_base; extern void __iomem *pll3_base; +extern void __iomem *pll4_base; #define MXC_CCM_BASE (IO_ADDRESS(CCM_BASE_ADDR)) #define MXC_DPLL1_BASE (pll1_base) #define MXC_DPLL2_BASE (pll2_base) #define MXC_DPLL3_BASE (pll3_base) +#define MXC_DPLL4_BASE (pll4_base) /* PLL Register Offsets */ #define MXC_PLL_DP_CTL 0x00 @@ -112,7 +114,8 @@ extern void __iomem *pll3_base; #define MXC_CCM_CCGR4 (MXC_CCM_BASE + 0x78) #define MXC_CCM_CCGR5 (MXC_CCM_BASE + 0x7C) #define MXC_CCM_CCGR6 (MXC_CCM_BASE + 0x80) -#define MXC_CCM_CMEOR (MXC_CCM_BASE + 0x84) +#define MXC_CCM_CCGR7 (MXC_CCM_BASE + 0x84) +#define MXC_CCM_CMEOR (MXC_CCM_BASE + 0x88) /* Define the bits in register CCR */ #define MXC_CCM_CCR_COSC_EN (1 << 12) @@ -124,9 +127,17 @@ extern void __iomem *pll3_base; #define MXC_CCM_CCR_OSCNT_MASK (0xFF) /* Define the bits in register CCDR */ +/* MX51 */ #define MXC_CCM_CCDR_HSC_HS_MASK (0x1 << 18) #define MXC_CCM_CCDR_IPU_HS_MASK (0x1 << 17) #define MXC_CCM_CCDR_EMI_HS_MASK (0x1 << 16) +/* MX53 */ +#define MXC_CCM_CCDR_IPU_HS_MX53_MASK (0x1 << 21) +#define MXC_CCM_CCDR_EMI_HS_INT2_MASK (0x1 << 20) +#define MXC_CCM_CCDR_EMI_HS_INT1_MASK (0x1 << 19) +#define MXC_CCM_CCDR_EMI_HS_SLOW_MASK (0x1 << 18) +#define MXC_CCM_CCDR_EMI_HS_FAST_MASK (0x1 << 17) +#define MXC_CCM_CCDR_EMI_HS_MASK (0x1 << 16) /* Define the bits in register CSR */ #define MXC_CCM_CSR_COSR_READY (1 << 5) @@ -134,10 +145,13 @@ extern void __iomem *pll3_base; #define MXC_CCM_CSR_CAMP2_READY (1 << 3) #define MXC_CCM_CSR_CAMP1_READY (1 << 2) #define MXC_CCM_CSR_FPM_READY (1 << 1) +#define MXC_CCM_CSR_TEMP_MON_ALARM (1 << 1) #define MXC_CCM_CSR_REF_EN_B (1 << 0) /* Define the bits in register CCSR */ #define MXC_CCM_CCSR_LP_APM_SEL (0x1 << 9) +#define MXC_CCM_CCSR_LP_APM_SEL_MX53 (0x1 << 10) +#define MXC_CCM_CCSR_PLL4_SW_CLK_SEL (1 << 9) #define MXC_CCM_CCSR_STEP_SEL_OFFSET (7) #define MXC_CCM_CCSR_STEP_SEL_MASK (0x3 << 7) #define MXC_CCM_CCSR_PLL2_PODF_OFFSET (5) @@ -179,6 +193,8 @@ extern void __iomem *pll3_base; #define MXC_CCM_CBCDR_PERCLK_PODF_MASK (0x7) /* Define the bits in register CBCMR */ +#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MX53_OFFSET (16) +#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MX53_MASK (0x3 << 16) #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET (14) #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14) #define MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET (12) @@ -207,12 +223,13 @@ extern void __iomem *pll3_base; #define MXC_CCM_CSCMR1_UART_CLK_SEL_MASK (0x3 << 24) #define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET (22) #define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK (0x3 << 22) -#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET (20) -#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK (0x3 << 20) -#define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL (0x1 << 19) +#define MXC_CCM_CSCMR1_ESDHC1_MSHC2_CLK_SEL_OFFSET (20) +#define MXC_CCM_CSCMR1_ESDHC1_MSHC2_CLK_SEL_MASK (0x3 << 20) +#define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL_MX51 (0x1 << 19) +#define MXC_CCM_CSCMR1_ESDHC2_CLK_SEL (0x1 << 19) #define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL (0x1 << 18) -#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET (16) -#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK (0x3 << 16) +#define MXC_CCM_CSCMR1_ESDHC3_MSHC2_CLK_SEL_OFFSET (16) +#define MXC_CCM_CSCMR1_ESDHC3_MSHC2_CLK_SEL_MASK (0x3 << 16) #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET (14) #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 14) #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET (12) @@ -237,6 +254,7 @@ extern void __iomem *pll3_base; #define MXC_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_MASK (0x3 << 24) #define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_OFFSET (22) #define MXC_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_MASK (0x3 << 22) +/* MX51 */ #define MXC_CCM_CSCMR2_ESC_CLK_SEL_OFFSET (20) #define MXC_CCM_CSCMR2_ESC_CLK_SEL_MASK (0x3 << 20) #define MXC_CCM_CSCMR2_HSC2_CLK_SEL_OFFSET (18) @@ -245,13 +263,29 @@ extern void __iomem *pll3_base; #define MXC_CCM_CSCMR2_HSC1_CLK_SEL_MASK (0x3 << 16) #define MXC_CCM_CSCMR2_HSI2C_CLK_SEL_OFFSET (14) #define MXC_CCM_CSCMR2_HSI2C_CLK_SEL_MASK (0x3 << 14) +/* MX53 */ +#define MXC_CCM_CSCMR2_ASRC_CLK_SEL (1<<21) +#define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET (19) +#define MXC_CCM_CSCMR2_ESAI_PRE_SEL_MASK (0x3 << 19) +#define MXC_CCM_CSCMR2_ESAI_POST_SEL_OFFSET (16) +#define MXC_CCM_CSCMR2_ESAI_POST_SEL_MASK (0x7 << 16) +#define MXC_CCM_CSCMR2_IEEE_CLK_SEL_OFFSET (14) +#define MXC_CCM_CSCMR2_IEEE_CLK_SEL_MASK (0x3 << 14) #define MXC_CCM_CSCMR2_FIRI_CLK_SEL_OFFSET (12) #define MXC_CCM_CSCMR2_FIRI_CLK_SEL_MASK (0x3 << 12) +/* MX51 */ #define MXC_CCM_CSCMR2_SIM_CLK_SEL_OFFSET (10) #define MXC_CCM_CSCMR2_SIM_CLK_SEL_MASK (0x3 << 10) #define MXC_CCM_CSCMR2_SLIMBUS_COM (0x1 << 9) #define MXC_CCM_CSCMR2_SLIMBUS_CLK_SEL_OFFSET (6) #define MXC_CCM_CSCMR2_SLIMBUS_CLK_SEL_MASK (0x7 << 6) +/* MX51 */ +#define MXC_CCM_CSCMR2_LBD_DI1_IPU_DIV (0x1 << 11) +#define MXC_CCM_CSCMR2_LBD_DI0_IPU_DIV (0x1 << 10) +#define MXC_CCM_CSCMR2_LBD_DI1_CLK_SEL (0x1 << 9) +#define MXC_CCM_CSCMR2_LBD_DI0_CLK_SEL (0x1 << 8) +#define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET (6) +#define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3 << 6) #define MXC_CCM_CSCMR2_SPDIF1_COM (1 << 5) #define MXC_CCM_CSCMR2_SPDIF0_COM (1 << 4) #define MXC_CCM_CSCMR2_SPDIF1_CLK_SEL_OFFSET (2) @@ -264,12 +298,16 @@ extern void __iomem *pll3_base; #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK (0x7 << 22) #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET (19) #define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK (0x7 << 19) -#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET (16) -#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK (0x7 << 16) +#define MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PRED_OFFSET (22) +#define MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PRED_MASK (0x7 << 22) +#define MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PODF_OFFSET (19) +#define MXC_CCM_CSCDR1_ESDHC3_MSHC2_CLK_PODF_MASK (0x7 << 19) +#define MXC_CCM_CSCDR1_ESDHC1_MSHC2_CLK_PRED_OFFSET (16) +#define MXC_CCM_CSCDR1_ESDHC1_MSHC2_CLK_PRED_MASK (0x7 << 16) #define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET (14) #define MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK (0x3 << 14) -#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET (11) -#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK (0x7 << 11) +#define MXC_CCM_CSCDR1_ESDHC1_MSHC2_CLK_PODF_OFFSET (11) +#define MXC_CCM_CSCDR1_ESDHC1_MSHC2_CLK_PODF_MASK (0x7 << 11) #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET (8) #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8) #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET (6) @@ -280,10 +318,14 @@ extern void __iomem *pll3_base; #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK (0x7) /* Define the bits in register CS1CDR and CS2CDR */ +#define MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET (25) +#define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK (0x3F << 25) #define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_OFFSET (22) #define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PRED_MASK (0x7 << 22) #define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_OFFSET (16) #define MXC_CCM_CS1CDR_SSI_EXT1_CLK_PODF_MASK (0x3F << 16) +#define MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET (9) +#define MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK (0x7 << 9) #define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET (6) #define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << 6) #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET (0) @@ -305,18 +347,23 @@ extern void __iomem *pll3_base; #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << 25) #define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET (19) #define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x3F << 19) +/* MX51 */ #define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET (16) #define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << 16) +/* MX53 */ +#define MXC_CCM_CDCDR_DI_PLL4_PODF_OFFSET (16) +#define MXC_CCM_CDCDR_DI_PLL4_PODF_MASK (0x7 << 16) #define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET (9) #define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x3F << 9) -#define MXC_CCM_CDCDR_DI_CLK_PRED_OFFSET (6) -#define MXC_CCM_CDCDR_DI_CLK_PRED_MASK (0x7 << 6) +#define MXC_CCM_CDCDR_DI1_CLK_PRED_OFFSET (6) +#define MXC_CCM_CDCDR_DI1_CLK_PRED_MASK (0x7 << 6) #define MXC_CCM_CDCDR_USB_PHY_PRED_OFFSET (3) #define MXC_CCM_CDCDR_USB_PHY_PRED_MASK (0x7 << 3) #define MXC_CCM_CDCDR_USB_PHY_PODF_OFFSET (0) #define MXC_CCM_CDCDR_USB_PHY_PODF_MASK (0x7) /* Define the bits in register CHSCCDR */ +/* MX51 */ #define MXC_CCM_CHSCCDR_ESC_CLK_PRED_OFFSET (12) #define MXC_CCM_CHSCCDR_ESC_CLK_PRED_MASK (0x7 << 12) #define MXC_CCM_CHSCCDR_ESC_CLK_PODF_OFFSET (6) @@ -325,12 +372,24 @@ extern void __iomem *pll3_base; #define MXC_CCM_CHSCCDR_HSC2_CLK_PODF_MASK (0x7 << 3) #define MXC_CCM_CHSCCDR_HSC1_CLK_PODF_OFFSET (0) #define MXC_CCM_CHSCCDR_HSC1_CLK_PODF_MASK (0x7) +/* MX53 */ +#define MXC_CCM_CHSCCDR_ESAI_HCKT_SEL_OFFSET (6) +#define MXC_CCM_CHSCCDR_ESAI_HCKT_SEL_MASK (0x3 << 6) +#define MXC_CCM_CHSCCDR_ESAI_HCKR_SEL_OFFSET (4) +#define MXC_CCM_CHSCCDR_ESAI_HCKR_SEL_MASK (0x3 << 4) +#define MXC_CCM_CHSCCDR_SSI2_MLB_SPDIF_SRC_OFFSET (2) +#define MXC_CCM_CHSCCDR_SSI2_MLB_SPDIF_SRC_MASK (0x3 << 2) +#define MXC_CCM_CHSCCDR_SSI1_MLB_SPDIF_SRC_OFFSET (0) +#define MXC_CCM_CHSCCDR_SSI1_MLB_SPDIF_SRC_MASK (0x3) /* Define the bits in register CSCDR2 */ +#define MXC_CCM_CSCDR2_ASRC_CLK_PRED_OFFSET (28) +#define MXC_CCM_CSCDR2_ASRC_CLK_PRED_MASK (0x7 << 28) #define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET (25) #define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK (0x7 << 25) #define MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET (19) #define MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK (0x3F << 19) +/* MX51 */ #define MXC_CCM_CSCDR2_SIM_CLK_PRED_OFFSET (16) #define MXC_CCM_CSCDR2_SIM_CLK_PRED_MASK (0x7 << 16) #define MXC_CCM_CSCDR2_SIM_CLK_PODF_OFFSET (9) @@ -339,6 +398,13 @@ extern void __iomem *pll3_base; #define MXC_CCM_CSCDR2_SLIMBUS_PRED_MASK (0x7 << 6) #define MXC_CCM_CSCDR2_SLIMBUS_PODF_OFFSET (0) #define MXC_CCM_CSCDR2_SLIMBUS_PODF_MASK (0x3F) +/* MX53 */ +#define MXC_CCM_CSCDR2_ASRC_CLK_PODF_OFFSET (9) +#define MXC_CCM_CSCDR2_ASRC_CLK_PODF_MASK (0x3F << 9) +#define MXC_CCM_CSCDR2_IEEE_CLK_PRED_OFFSET (6) +#define MXC_CCM_CSCDR2_IEEE_CLK_PRED_MASK (0x7 << 6) +#define MXC_CCM_CSCDR2_IEEE_CLK_PODF_OFFSET (0) +#define MXC_CCM_CSCDR2_IEEE_CLK_PODF_MASK (0x3F) /* Define the bits in register CSCDR3 */ #define MXC_CCM_CSCDR3_HSI2C_CLK_PRED_OFFSET (16) @@ -378,10 +444,21 @@ extern void __iomem *pll3_base; #define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_MASK (0x3) /* Define the bits in register CLPCR */ +/* MX51 */ #define MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS (0x1 << 23) -#define MXC_CCM_CLPCR_BYPASS_SCC_LPM_HS (0x1 << 22) -#define MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS (0x1 << 21) -#define MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS (0x1 << 20) +#define MXC_CCM_CLPCR_BYPASS_SCC_LPM_HS_MX51 (0x1 << 22) +#define MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS_MX51 (0x1 << 21) +#define MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS_MX51 (0x1 << 20) +/* MX53 */ +#define MXC_CCM_CLPCR_BYPASS_CAN2_LPM_HS (0x1 << 27) +#define MXC_CCM_CLPCR_BYPASS_CAN1_LPM_HS (0x1 << 27) +#define MXC_CCM_CLPCR_BYPASS_SCC_LPM_HS_MX53 (0x1 << 26) +#define MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS_MX53 (0x1 << 25) +#define MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS_MX53 (0x1 << 24) +#define MXC_CCM_CLPCR_BYPASS_EMI_INT2_LPM_HS (0x1 << 23) +#define MXC_CCM_CLPCR_BYPASS_EMI_INT1_LPM_HS (0x1 << 22) +#define MXC_CCM_CLPCR_BYPASS_EMI_SLOW_LPM_HS (0x1 << 21) +#define MXC_CCM_CLPCR_BYPASS_EMI_FAST_LPM_HS (0x1 << 20) #define MXC_CCM_CLPCR_BYPASS_EMI_LPM_HS (0x1 << 19) #define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS (0x1 << 18) #define MXC_CCM_CLPCR_BYPASS_RTIC_LPM_HS (0x1 << 17) @@ -399,7 +476,11 @@ extern void __iomem *pll3_base; #define MXC_CCM_CLPCR_LPM_MASK (0x3) /* Define the bits in register CISR */ -#define MXC_CCM_CISR_ARM_PODF_LOADED (0x1 << 25) +#define MXC_CCM_CISR_ARM_PODF_LOADED_MX51 (0x1 << 25) +#define MXC_CCM_CISR_ARM_PODF_LOADED_MX53 (0x1 << 26) +#define MXC_CCM_CISR_TEMP_MON_ALARM (0x1 << 25) +#define MXC_CCM_CISR_EMI_CLK_SEL_LOADED (0x1 << 23) +#define MXC_CCM_CISR_PER_CLK_SEL_LOADED (0x1 << 22) #define MXC_CCM_CISR_NFC_IPG_INT_MEM_PODF_LOADED (0x1 << 21) #define MXC_CCM_CISR_AHB_PODF_LOADED (0x1 << 20) #define MXC_CCM_CISR_EMI_PODF_LOADED (0x1 << 19) @@ -415,16 +496,28 @@ extern void __iomem *pll3_base; #define MXC_CCM_CISR_LRF_PLL1 (0x1) /* Define the bits in register CIMR */ -#define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (0x1 << 25) +#define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED_MX51 (0x1 << 25) +#define MXC_CCM_CIMR_MASK_EMI_PODF_LOADED_MX51 (0x1 << 20) +#define MXC_CCM_CIMR_MASK_AXI_C_PODF_LOADED_MX51 (0x1 << 19) +#define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED_MX53 (0x1 << 26) +#define MXC_CCM_CIMR_MASK_TEMP_MON_ALARM (0x1 << 25) +#define MXC_CCM_CIMR_MASK_EMI_CLK_SEL_LOADED (0x1 << 23) +#define MXC_CCM_CIMR_MASK_PER_CLK_SEL_LOADED (0x1 << 22) #define MXC_CCM_CIMR_MASK_NFC_IPG_INT_MEM_PODF_LOADED (0x1 << 21) -#define MXC_CCM_CIMR_MASK_EMI_PODF_LOADED (0x1 << 20) -#define MXC_CCM_CIMR_MASK_AXI_C_PODF_LOADED (0x1 << 19) +#define MXC_CCM_CIMR_MASK_AHB_PODF_LOADED_MX53 (0x1 << 20) +#define MXC_CCM_CIMR_MASK_EMI_SLOW_PODF_LOADED_MX53 (0x1 << 19) #define MXC_CCM_CIMR_MASK_AXI_B_PODF_LOADED (0x1 << 18) #define MXC_CCM_CIMR_MASK_AXI_A_PODF_LOADED (0x1 << 17) #define MXC_CCM_CIMR_MASK_DIVIDER_LOADED (0x1 << 16) -#define MXC_CCM_CIMR_MASK_COSC_READY (0x1 << 5) +/* MX51 */ +#define MXC_CCM_CIMR_MASK_COSC_READY_MX51 (0x1 << 5) #define MXC_CCM_CIMR_MASK_CKIH_READY (0x1 << 4) #define MXC_CCM_CIMR_MASK_FPM_READY (0x1 << 3) +/* MX53 */ +#define MXC_CCM_CIMR_MASK_COSC_READY_MX53 (0x1 << 6) +#define MXC_CCM_CIMR_MASK_CAMP2_READY (0x1 << 5) +#define MXC_CCM_CIMR_MASK_CAMP1_READY (0x1 << 4) +#define MXC_CCM_CIMR_MASK_LRF_PLL4 (0x1 << 3) #define MXC_CCM_CIMR_MASK_LRF_PLL3 (0x1 << 2) #define MXC_CCM_CIMR_MASK_LRF_PLL2 (0x1 << 1) #define MXC_CCM_CIMR_MASK_LRF_PLL1 (0x1) @@ -442,6 +535,8 @@ extern void __iomem *pll3_base; #define MXC_CCM_CCOSR_CKOL_SEL_MASK (0xF) /* Define the bits in registers CGPR */ +#define MXC_CCM_CGPR_ARM_CLK_INPUT_SEL (0x1 << 24) +#define MXC_CCM_CGPR_ARM_ASYNC_REF_EN (0x1 << 23) #define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (0x1 << 4) #define MXC_CCM_CGPR_FPM_SEL (0x1 << 3) #define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_OFFSET (0) @@ -568,6 +663,8 @@ extern void __iomem *pll3_base; #define MXC_CCM_CCGR5_CG7_MASK (0x3 << 14) #define MXC_CCM_CCGR5_CG6_1_OFFSET 12 #define MXC_CCM_CCGR5_CG6_2_OFFSET 13 +#define MXC_CCM_CCGR5_CG6_OFFSET 12 +#define MXC_CCM_CCGR5_CG6_MASK (0x3 << 12) #define MXC_CCM_CCGR5_CG5_OFFSET 10 #define MXC_CCM_CCGR5_CG4_OFFSET 8 #define MXC_CCM_CCGR5_CG3_OFFSET 6 @@ -575,6 +672,22 @@ extern void __iomem *pll3_base; #define MXC_CCM_CCGR5_CG2_MASK (0x3 << 4) #define MXC_CCM_CCGR5_CG1_OFFSET 2 #define MXC_CCM_CCGR5_CG0_OFFSET 0 + +#define MXC_CCM_CCGR6_CG15_OFFSET 30 +#define MXC_CCM_CCGR6_CG14_OFFSET 28 +#define MXC_CCM_CCGR6_CG14_MASK (0x3 << 28) +#define MXC_CCM_CCGR6_CG13_OFFSET 26 +#define MXC_CCM_CCGR6_CG13_MASK (0x3 << 26) +#define MXC_CCM_CCGR6_CG12_OFFSET 24 +#define MXC_CCM_CCGR6_CG12_MASK (0x3 << 24) +#define MXC_CCM_CCGR6_CG11_OFFSET 22 +#define MXC_CCM_CCGR6_CG11_MASK (0x3 << 22) +#define MXC_CCM_CCGR6_CG10_OFFSET 20 +#define MXC_CCM_CCGR6_CG10_MASK (0x3 << 20) +#define MXC_CCM_CCGR6_CG9_OFFSET 18 +#define MXC_CCM_CCGR6_CG9_MASK (0x3 << 18) +#define MXC_CCM_CCGR6_CG8_OFFSET 16 +#define MXC_CCM_CCGR6_CG8_MASK (0x3 << 16) #define MXC_CCM_CCGR6_CG7_OFFSET 14 #define MXC_CCM_CCGR6_CG7_MASK (0x3 << 14) #define MXC_CCM_CCGR6_CG6_OFFSET 12 @@ -585,9 +698,37 @@ extern void __iomem *pll3_base; #define MXC_CCM_CCGR6_CG4_MASK (0x3 << 8) #define MXC_CCM_CCGR6_CG3_OFFSET 6 #define MXC_CCM_CCGR6_CG2_OFFSET 4 +#define MXC_CCM_CCGR6_CG2_MASK (0x3 << 4) #define MXC_CCM_CCGR6_CG1_OFFSET 2 #define MXC_CCM_CCGR6_CG0_OFFSET 0 +#define MXC_CCM_CCGR7_CG15_OFFSET 30 +#define MXC_CCM_CCGR7_CG14_OFFSET 28 +#define MXC_CCM_CCGR7_CG14_MASK (0x3 << 28) +#define MXC_CCM_CCGR7_CG13_OFFSET 26 +#define MXC_CCM_CCGR7_CG13_MASK (0x3 << 26) +#define MXC_CCM_CCGR7_CG12_OFFSET 24 +#define MXC_CCM_CCGR7_CG12_MASK (0x3 << 24) +#define MXC_CCM_CCGR7_CG11_OFFSET 22 +#define MXC_CCM_CCGR7_CG11_MASK (0x3 << 22) +#define MXC_CCM_CCGR7_CG10_OFFSET 20 +#define MXC_CCM_CCGR7_CG10_MASK (0x3 << 20) +#define MXC_CCM_CCGR7_CG9_OFFSET 18 +#define MXC_CCM_CCGR7_CG9_MASK (0x3 << 18) +#define MXC_CCM_CCGR7_CG8_OFFSET 16 +#define MXC_CCM_CCGR7_CG8_MASK (0x3 << 16) +#define MXC_CCM_CCGR7_CG7_OFFSET 14 +#define MXC_CCM_CCGR7_CG7_MASK (0x3 << 14) +#define MXC_CCM_CCGR7_CG6_OFFSET 12 +#define MXC_CCM_CCGR7_CG6_MASK (0x3 << 12) +#define MXC_CCM_CCGR7_CG5_OFFSET 10 +#define MXC_CCM_CCGR7_CG4_OFFSET 8 +#define MXC_CCM_CCGR7_CG3_OFFSET 6 +#define MXC_CCM_CCGR7_CG2_OFFSET 4 +#define MXC_CCM_CCGR7_CG2_MASK (0x3 << 4) +#define MXC_CCM_CCGR7_CG1_OFFSET 2 +#define MXC_CCM_CCGR7_CG0_OFFSET 0 + #define MXC_GPC_BASE (IO_ADDRESS(GPC_BASE_ADDR)) #define MXC_DPTC_LP_BASE (MXC_GPC_BASE + 0x80) #define MXC_DPTC_GP_BASE (MXC_GPC_BASE + 0x100) diff --git a/arch/arm/mach-mx5/devices.c b/arch/arm/mach-mx5/devices.c index bcf7da7d36a3..c83bdd9078d9 100644 --- a/arch/arm/mach-mx5/devices.c +++ b/arch/arm/mach-mx5/devices.c @@ -25,7 +25,6 @@ #include <mach/hardware.h> #include <mach/gpio.h> #include <mach/sdma.h> -#include "sdma_script_code.h" #include "crm_regs.h" /* Flag used to indicate when IRAM has been initialized */ @@ -33,68 +32,6 @@ int iram_ready; /* Flag used to indicate if dvfs_core is active. */ int dvfs_core_is_active; -void mxc_sdma_get_script_info(sdma_script_start_addrs * sdma_script_addr) -{ - /* AP<->BP */ - sdma_script_addr->mxc_sdma_ap_2_ap_addr = ap_2_ap_ADDR; - sdma_script_addr->mxc_sdma_ap_2_bp_addr = -1; - sdma_script_addr->mxc_sdma_bp_2_ap_addr = -1; - sdma_script_addr->mxc_sdma_ap_2_ap_fixed_addr = -1; - - /*misc */ - sdma_script_addr->mxc_sdma_loopback_on_dsp_side_addr = -1; - sdma_script_addr->mxc_sdma_mcu_interrupt_only_addr = -1; - - /* firi */ - sdma_script_addr->mxc_sdma_firi_2_per_addr = -1; - sdma_script_addr->mxc_sdma_firi_2_mcu_addr = -1; - sdma_script_addr->mxc_sdma_per_2_firi_addr = -1; - sdma_script_addr->mxc_sdma_mcu_2_firi_addr = -1; - - /* uart */ - sdma_script_addr->mxc_sdma_uart_2_per_addr = uart_2_per_ADDR; - sdma_script_addr->mxc_sdma_uart_2_mcu_addr = uart_2_mcu_ADDR; - - /* UART SH */ - sdma_script_addr->mxc_sdma_uartsh_2_per_addr = uartsh_2_per_ADDR; - sdma_script_addr->mxc_sdma_uartsh_2_mcu_addr = uartsh_2_mcu_ADDR; - - /* SHP */ - sdma_script_addr->mxc_sdma_per_2_shp_addr = per_2_shp_ADDR; - sdma_script_addr->mxc_sdma_shp_2_per_addr = shp_2_per_ADDR; - sdma_script_addr->mxc_sdma_mcu_2_shp_addr = mcu_2_shp_ADDR; - sdma_script_addr->mxc_sdma_shp_2_mcu_addr = shp_2_mcu_ADDR; - - /* ATA */ - sdma_script_addr->mxc_sdma_mcu_2_ata_addr = mcu_2_ata_ADDR; - sdma_script_addr->mxc_sdma_ata_2_mcu_addr = ata_2_mcu_ADDR; - - /* app */ - sdma_script_addr->mxc_sdma_app_2_per_addr = app_2_per_ADDR; - sdma_script_addr->mxc_sdma_app_2_mcu_addr = app_2_mcu_ADDR; - sdma_script_addr->mxc_sdma_per_2_app_addr = per_2_app_ADDR; - sdma_script_addr->mxc_sdma_mcu_2_app_addr = mcu_2_app_ADDR; - - /* MSHC */ - sdma_script_addr->mxc_sdma_mshc_2_mcu_addr = -1; - sdma_script_addr->mxc_sdma_mcu_2_mshc_addr = -1; - - /* spdif */ - sdma_script_addr->mxc_sdma_spdif_2_mcu_addr = -1; - sdma_script_addr->mxc_sdma_mcu_2_spdif_addr = mcu_2_spdif_ADDR; - - /* IPU */ - sdma_script_addr->mxc_sdma_ext_mem_2_ipu_addr = ext_mem__ipu_ram_ADDR; - - /* DVFS */ - sdma_script_addr->mxc_sdma_dptc_dvfs_addr = -1; - - /* core */ - sdma_script_addr->mxc_sdma_start_addr = (unsigned short *)sdma_code; - sdma_script_addr->mxc_sdma_ram_code_start_addr = RAM_CODE_START_ADDR; - sdma_script_addr->mxc_sdma_ram_code_size = RAM_CODE_SIZE; -} - static struct resource sdma_resources[] = { { .start = SDMA_BASE_ADDR, @@ -183,14 +120,14 @@ struct platform_device mxc_nandv2_mtd_device = { static struct resource imx_nfc_resources[] = { { .flags = IORESOURCE_MEM, - .start = NFC_BASE_ADDR_AXI + 0x0000, - .end = NFC_BASE_ADDR_AXI + 0x1200 - 1, + .start = MX51_NFC_BASE_ADDR_AXI, + .end = MX51_NFC_BASE_ADDR_AXI + 0x1200 - 1, .name = IMX_NFC_BUFFERS_ADDR_RES_NAME, }, { .flags = IORESOURCE_MEM, - .start = NFC_BASE_ADDR_AXI + 0x1E00, - .end = NFC_BASE_ADDR_AXI + 0x1E44 - 1, + .start = MX51_NFC_BASE_ADDR_AXI + 0x1E00, + .end = MX51_NFC_BASE_ADDR_AXI + 0x1E44 - 1, .name = IMX_NFC_PRIMARY_REGS_ADDR_RES_NAME, }, { @@ -276,8 +213,8 @@ struct platform_device mxc_pwm_backlight_device = { static struct resource ipu_resources[] = { { - .start = IPU_CTRL_BASE_ADDR, - .end = IPU_CTRL_BASE_ADDR + SZ_512M, + .start = MX51_IPU_CTRL_BASE_ADDR, + .end = MX51_IPU_CTRL_BASE_ADDR + SZ_512M, .flags = IORESOURCE_MEM, }, { @@ -447,6 +384,18 @@ static struct resource mxci2c2_resources[] = { }, }; +static struct resource mxci2c3_resources[] = { + { + .start = I2C3_BASE_ADDR, + .end = I2C3_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = MXC_INT_I2C3, + .end = MXC_INT_I2C3, + .flags = IORESOURCE_IRQ, + }, +}; struct platform_device mxci2c_devices[] = { { @@ -461,6 +410,12 @@ struct platform_device mxci2c_devices[] = { .num_resources = ARRAY_SIZE(mxci2c2_resources), .resource = mxci2c2_resources, }, + { + .name = "mxc_i2c", + .id = 2, + .num_resources = ARRAY_SIZE(mxci2c3_resources), + .resource = mxci2c3_resources, + }, }; static struct resource mxci2c_hs_resources[] = { @@ -611,10 +566,33 @@ struct mxc_gpio_port mxc_gpio_ports[] = { .irq_high = MXC_INT_GPIO4_HIGH, .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 3 }, + { + .chip.label = "gpio-4", + .base = IO_ADDRESS(GPIO5_BASE_ADDR), + .irq = MXC_INT_GPIO5_LOW, + .irq_high = MXC_INT_GPIO5_HIGH, + .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 4 + }, + { + .chip.label = "gpio-5", + .base = IO_ADDRESS(GPIO6_BASE_ADDR), + .irq = MXC_INT_GPIO6_LOW, + .irq_high = MXC_INT_GPIO6_HIGH, + .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 5 + }, + { + .chip.label = "gpio-6", + .base = IO_ADDRESS(GPIO7_BASE_ADDR), + .irq = MXC_INT_GPIO7_LOW, + .irq_high = MXC_INT_GPIO7_HIGH, + .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 6 + }, }; int __init mxc_register_gpios(void) { + if (cpu_is_mx51()) + return mxc_gpio_init(mxc_gpio_ports, 4); return mxc_gpio_init(mxc_gpio_ports, ARRAY_SIZE(mxc_gpio_ports)); } @@ -625,8 +603,8 @@ static struct resource spdif_resources[] = { .flags = IORESOURCE_MEM, }, { - .start = MXC_INT_SPDIF, - .end = MXC_INT_SPDIF, + .start = MXC_INT_SPDIF_MX51, + .end = MXC_INT_SPDIF_MX51, .flags = IORESOURCE_IRQ, }, }; @@ -735,6 +713,22 @@ static struct resource mxcsdhc2_resources[] = { }, }; +static struct resource mxcsdhc3_resources[] = { + { + .start = MMC_SDHC3_BASE_ADDR, + .end = MMC_SDHC3_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = MXC_INT_MMC_SDHC3, + .end = MXC_INT_MMC_SDHC3, + .flags = IORESOURCE_IRQ, + }, + { + .flags = IORESOURCE_IRQ, + }, +}; + struct platform_device mxcsdhc1_device = { .name = "mxsdhci", .id = 0, @@ -749,6 +743,13 @@ struct platform_device mxcsdhc2_device = { .resource = mxcsdhc2_resources, }; +struct platform_device mxcsdhc3_device = { + .name = "mxsdhci", + .id = 2, + .num_resources = ARRAY_SIZE(mxcsdhc3_resources), + .resource = mxcsdhc3_resources, +}; + static struct resource pata_fsl_resources[] = { { .start = ATA_BASE_ADDR, @@ -891,8 +892,8 @@ static struct resource mxc_gpu_resources[] = { .flags = IORESOURCE_IRQ, }, { - .start = GPU2D_BASE_ADDR, - .end = GPU2D_BASE_ADDR + SZ_4K - 1, + .start = MX51_GPU2D_BASE_ADDR, + .end = MX51_GPU2D_BASE_ADDR + SZ_4K - 1, .name = "gpu_2d_registers", .flags = IORESOURCE_MEM, }, @@ -903,8 +904,8 @@ static struct resource mxc_gpu_resources[] = { .flags = IORESOURCE_MEM, }, { - .start = GPU_GMEM_BASE_ADDR, - .end = GPU_GMEM_BASE_ADDR + SZ_128K - 1, + .start = MX51_GPU_GMEM_BASE_ADDR, + .end = MX51_GPU_GMEM_BASE_ADDR + SZ_128K - 1, .name = "gpu_graphics_mem", .flags = IORESOURCE_MEM, }, @@ -919,8 +920,8 @@ struct platform_device gpu_device = { static struct resource mxc_gpu2d_resources[] = { { - .start = GPU2D_BASE_ADDR, - .end = GPU2D_BASE_ADDR + SZ_4K - 1, + .start = MX51_GPU2D_BASE_ADDR, + .end = MX51_GPU2D_BASE_ADDR + SZ_4K - 1, .flags = IORESOURCE_MEM, }, { @@ -1004,14 +1005,16 @@ static inline void mxc_init_gpu2d(void) } #endif -void __init mx51_init_irq(void) +void __init mx5_init_irq(void) { unsigned long tzic_addr; if (cpu_is_mx51_rev(CHIP_REV_2_0) < 0) - tzic_addr = TZIC_BASE_ADDR_T01; - else - tzic_addr = TZIC_BASE_ADDR; + tzic_addr = MX51_TZIC_BASE_ADDR_T01; + else if (cpu_is_mx51_rev(CHIP_REV_2_0) > 0) + tzic_addr = MX51_TZIC_BASE_ADDR; + else /* mx53 */ + tzic_addr = MX53_TZIC_BASE_ADDR; mxc_tzic_init_irq(tzic_addr); } @@ -1036,6 +1039,9 @@ static __init void mxc_init_scc_iram(void) long cur_ns = 0; long start_ns = 0; + if (!cpu_is_mx51()) + return; + if (cpu_is_mx51_rev(CHIP_REV_2_0) < 0) iram_partitions = 12; @@ -1044,7 +1050,7 @@ static __init void mxc_init_scc_iram(void) printk(KERN_ERR "FAILED TO MAP IRAM REGS\n"); return; } - scm_ram_base = ioremap((uint32_t) IRAM_BASE_ADDR, IRAM_SIZE); + scm_ram_base = ioremap((uint32_t) MX51_IRAM_BASE_ADDR, IRAM_SIZE); if (scm_ram_base == NULL) { printk(KERN_ERR "FAILED TO MAP IRAM\n"); return; @@ -1196,8 +1202,87 @@ static __init void mxc_init_scc_iram(void) iram_ready = 1; } +#define MX53_OFFSET 0x20000000 + int __init mxc_init_devices(void) { + if (cpu_is_mx53()) { + sdma_resources[0].start -= MX53_OFFSET; + sdma_resources[0].end -= MX53_OFFSET; + mxc_w1_master_resources[0].start -= MX53_OFFSET; + mxc_w1_master_resources[0].end -= MX53_OFFSET; + mxc_kpp_resources[0].start -= MX53_OFFSET; + mxc_kpp_resources[0].end -= MX53_OFFSET; + rtc_resources[0].start -= MX53_OFFSET; + rtc_resources[0].end -= MX53_OFFSET; + imx_nfc_resources[0].start = MX53_NFC_BASE_ADDR_AXI; + imx_nfc_resources[0].end = MX53_NFC_BASE_ADDR_AXI + 0x1200 - 1; + imx_nfc_resources[1].start = MX53_NFC_BASE_ADDR_AXI + 0x1E00; + imx_nfc_resources[1].end = MX53_NFC_BASE_ADDR_AXI + 0x1E44 - 1; + imx_nfc_resources[2].start -= MX53_OFFSET; + imx_nfc_resources[2].end -= MX53_OFFSET; + wdt_resources[0].start -= MX53_OFFSET; + wdt_resources[0].end -= MX53_OFFSET; + pwm1_resources[0].start -= MX53_OFFSET; + pwm1_resources[0].end -= MX53_OFFSET; + pwm2_resources[0].start -= MX53_OFFSET; + pwm2_resources[0].end -= MX53_OFFSET; + mxc_fec_resources[0].start -= MX53_OFFSET; + mxc_fec_resources[0].end -= MX53_OFFSET; + mxcspi1_resources[0].start -= MX53_OFFSET; + mxcspi1_resources[0].end -= MX53_OFFSET; + mxcspi2_resources[0].start -= MX53_OFFSET; + mxcspi2_resources[0].end -= MX53_OFFSET; + mxcspi3_resources[0].start -= MX53_OFFSET; + mxcspi3_resources[0].end -= MX53_OFFSET; + mxci2c1_resources[0].start -= MX53_OFFSET; + mxci2c1_resources[0].end -= MX53_OFFSET; + mxci2c2_resources[0].start -= MX53_OFFSET; + mxci2c2_resources[0].end -= MX53_OFFSET; + mxci2c3_resources[0].start -= MX53_OFFSET; + mxci2c3_resources[0].end -= MX53_OFFSET; + ssi1_resources[0].start -= MX53_OFFSET; + ssi1_resources[0].end -= MX53_OFFSET; + ssi2_resources[0].start -= MX53_OFFSET; + ssi2_resources[0].end -= MX53_OFFSET; + tve_resources[0].start -= MX53_OFFSET; + tve_resources[0].end -= MX53_OFFSET; + dvfs_per_resources[0].start -= MX53_OFFSET; + dvfs_per_resources[0].end -= MX53_OFFSET; + spdif_resources[0].start -= MX53_OFFSET; + spdif_resources[0].end -= MX53_OFFSET; + spdif_resources[1].start = MXC_INT_SPDIF_MX53; + spdif_resources[1].end = MXC_INT_SPDIF_MX53; + mxc_m4if_resources[0].start -= MX53_OFFSET; + mxc_m4if_resources[0].end -= MX53_OFFSET; + mxc_iim_resources[0].start -= MX53_OFFSET; + mxc_iim_resources[0].end -= MX53_OFFSET; + mxc_sim_resources[0].start -= MX53_OFFSET; + mxc_sim_resources[0].end -= MX53_OFFSET; + mxcsdhc1_resources[0].start -= MX53_OFFSET; + mxcsdhc1_resources[0].end -= MX53_OFFSET; + mxcsdhc2_resources[0].start -= MX53_OFFSET; + mxcsdhc2_resources[0].end -= MX53_OFFSET; + mxcsdhc3_resources[0].start -= MX53_OFFSET; + mxcsdhc3_resources[0].end -= MX53_OFFSET; + usbotg_resources[0].start -= MX53_OFFSET; + usbotg_resources[0].end -= MX53_OFFSET; + usbotg_xcvr_resources[0].start -= MX53_OFFSET; + usbotg_xcvr_resources[0].end -= MX53_OFFSET; + usbh1_resources[0].start -= MX53_OFFSET; + usbh1_resources[0].end -= MX53_OFFSET; + usbh2_resources[0].start -= MX53_OFFSET; + usbh2_resources[0].end -= MX53_OFFSET; + mxc_gpu_resources[2].start = MX53_GPU2D_BASE_ADDR; + mxc_gpu_resources[2].end = MX53_GPU2D_BASE_ADDR + SZ_4K - 1; + mxc_gpu_resources[4].start = MX53_GPU_GMEM_BASE_ADDR; + mxc_gpu_resources[4].end = MX53_GPU_GMEM_BASE_ADDR + SZ_256K - 1; + mxc_gpu2d_resources[0].start = MX53_GPU2D_BASE_ADDR; + mxc_gpu2d_resources[0].end = MX53_GPU2D_BASE_ADDR + SZ_4K - 1; + ipu_resources[0].start = MX53_IPU_CTRL_BASE_ADDR; + ipu_resources[0].end = MX53_IPU_CTRL_BASE_ADDR + SZ_128M - 1; + } + mxc_init_scc_iram(); mxc_init_gpu2d(); return 0; diff --git a/arch/arm/mach-mx5/devices.h b/arch/arm/mach-mx5/devices.h index 5a600527511a..52b79f7dab40 100644 --- a/arch/arm/mach-mx5/devices.h +++ b/arch/arm/mach-mx5/devices.h @@ -42,12 +42,14 @@ extern struct platform_device mxc_ssi1_device; extern struct platform_device mxc_ssi2_device; extern struct platform_device mxc_alsa_spdif_device; extern struct platform_device mx51_lpmode_device; +extern struct platform_device mx53_lpmode_device; extern struct platform_device busfreq_device; extern struct platform_device sdram_autogating_device; extern struct platform_device mxc_iim_device; extern struct platform_device mxc_sim_device; extern struct platform_device mxcsdhc1_device; extern struct platform_device mxcsdhc2_device; +extern struct platform_device mxcsdhc3_device; extern struct platform_device pata_fsl_device; extern struct platform_device gpu_device; extern struct platform_device mxc_fec_device; diff --git a/arch/arm/mach-mx5/dma.c b/arch/arm/mach-mx5/dma.c index a27d7e2a2349..b79fab73e41f 100644 --- a/arch/arm/mach-mx5/dma.c +++ b/arch/arm/mach-mx5/dma.c @@ -1,5 +1,5 @@ /* - * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. */ /* @@ -16,6 +16,8 @@ #include <mach/hardware.h> #include "serial.h" +#include "sdma_script_code.h" +#include "sdma_script_code_mx53.h" #define MXC_MMC_BUFFER_ACCESS 0x20 #define MXC_SDHC_MMC_WML 64 @@ -27,11 +29,23 @@ #define MXC_SSI_TXFIFO_WML 0x4 #define MXC_SSI_RXFIFO_WML 0x6 #define MXC_SPDIF_TXFIFO_WML 0x8 +#define MXC_SPDIF_RXFIFO_WML 0x8 #define MXC_SPDIF_TX_REG 0x2C +#define MXC_SPDIF_RX_REG 0x14 +#define MXC_ASRC_FIFO_WML 0x40 +#define MXC_ASRCA_RX_REG 0x60 +#define MXC_ASRCA_TX_REG 0x64 +#define MXC_ASRCB_RX_REG 0x68 +#define MXC_ASRCB_TX_REG 0x6C +#define MXC_ASRCC_RX_REG 0x70 +#define MXC_ASRCC_TX_REG 0x74 +#define MXC_ESAI_TX_REG 0x00 +#define MXC_ESAI_RX_REG 0x04 +#define MXC_ESAI_FIFO_WML 0x40 typedef struct mxc_sdma_info_entry_s { mxc_dma_device_t device; - mxc_sdma_channel_params_t *chnl_info; + void *chnl_info; } mxc_sdma_info_entry_t; static mxc_sdma_channel_params_t mxc_sdma_uart1_rx_params = { @@ -96,7 +110,7 @@ static mxc_sdma_channel_params_t mxc_sdma_uart3_rx_params = { .per_address = UART3_BASE_ADDR, .peripheral_type = UART_SP, .transfer_type = per_2_emi, - .event_id = DMA_REQ_UART3_RX, + .event_id = DMA_REQ_UART3_RX_MX51, .bd_number = 32, .word_size = TRANSFER_8BIT, }, @@ -110,7 +124,7 @@ static mxc_sdma_channel_params_t mxc_sdma_uart3_tx_params = { .per_address = UART3_BASE_ADDR + MXC_UARTUTXD, .peripheral_type = UART_SP, .transfer_type = emi_2_per, - .event_id = DMA_REQ_UART3_TX, + .event_id = DMA_REQ_UART3_TX_MX51, .bd_number = 32, .word_size = TRANSFER_8BIT, }, @@ -118,6 +132,62 @@ static mxc_sdma_channel_params_t mxc_sdma_uart3_tx_params = { .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, }; +static mxc_sdma_channel_params_t mxc_sdma_uart4_rx_params = { + .chnl_params = { + .watermark_level = UART4_UFCR_RXTL, + .per_address = UART4_BASE_ADDR, + .peripheral_type = UART, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_ATA_RX, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_UART4_RX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_uart4_tx_params = { + .chnl_params = { + .watermark_level = UART4_UFCR_TXTL, + .per_address = UART4_BASE_ADDR + MXC_UARTUTXD, + .peripheral_type = UART, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_ATA_TX, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_UART4_TX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_uart5_rx_params = { + .chnl_params = { + .watermark_level = UART5_UFCR_RXTL, + .per_address = UART5_BASE_ADDR, + .peripheral_type = UART, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_UART5_RX, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_UART5_RX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_uart5_tx_params = { + .chnl_params = { + .watermark_level = UART5_UFCR_TXTL, + .per_address = UART5_BASE_ADDR + MXC_UARTUTXD, + .peripheral_type = UART, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_UART5_TX, + .bd_number = 32, + .word_size = TRANSFER_8BIT, + }, + .channel_num = MXC_DMA_CHANNEL_UART5_TX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + static mxc_sdma_channel_params_t mxc_sdma_mmc1_width1_params = { .chnl_params = { .watermark_level = MXC_SDHC_MMC_WML, @@ -561,7 +631,7 @@ static mxc_sdma_channel_params_t mxc_sdma_spdif_16bit_tx_params = { .per_address = SPDIF_BASE_ADDR + MXC_SPDIF_TX_REG, .peripheral_type = SPDIF, .transfer_type = emi_2_per, - .event_id = DMA_REQ_SPDIF, + .event_id = DMA_REQ_SPDIF_MX51, .bd_number = 32, .word_size = TRANSFER_16BIT, }, @@ -575,7 +645,7 @@ static mxc_sdma_channel_params_t mxc_sdma_spdif_32bit_tx_params = { .per_address = SPDIF_BASE_ADDR + MXC_SPDIF_TX_REG, .peripheral_type = SPDIF, .transfer_type = emi_2_per, - .event_id = DMA_REQ_SPDIF, + .event_id = DMA_REQ_SPDIF_MX51, .bd_number = 32, .word_size = TRANSFER_32BIT, }, @@ -583,6 +653,442 @@ static mxc_sdma_channel_params_t mxc_sdma_spdif_32bit_tx_params = { .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, }; +static mxc_sdma_channel_params_t mxc_sdma_spdif_32bit_rx_params = { + .chnl_params = { + .watermark_level = MXC_SPDIF_RXFIFO_WML, + .per_address = SPDIF_BASE_ADDR + MXC_SPDIF_RX_REG, + .peripheral_type = SPDIF, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_SPDIF_RX, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_SPDIF_RX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_asrca_rx_params = { + .chnl_params = { + .watermark_level = MXC_ASRC_FIFO_WML, + .per_address = ASRC_BASE_ADDR + MXC_ASRCA_RX_REG, + .peripheral_type = ASRC, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_ASRC_DMA1, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_ASRCA_RX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_asrca_tx_params = { + .chnl_params = { + .watermark_level = MXC_ASRC_FIFO_WML, + .per_address = ASRC_BASE_ADDR + MXC_ASRCA_TX_REG, + .peripheral_type = ASRC, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_ASRC_DMA4, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_ASRCA_TX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_asrcb_rx_params = { + .chnl_params = { + .watermark_level = MXC_ASRC_FIFO_WML, + .per_address = ASRC_BASE_ADDR + MXC_ASRCB_RX_REG, + .peripheral_type = ASRC, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_ASRC_DMA2, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_ASRCB_RX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_asrcb_tx_params = { + .chnl_params = { + .watermark_level = MXC_ASRC_FIFO_WML, + .per_address = ASRC_BASE_ADDR + MXC_ASRCB_TX_REG, + .peripheral_type = ASRC, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_ASRC_DMA5, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_ASRCB_TX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_asrcc_rx_params = { + .chnl_params = { + .watermark_level = MXC_ASRC_FIFO_WML * 3, + .per_address = ASRC_BASE_ADDR + MXC_ASRCC_RX_REG, + .peripheral_type = ASRC, + .transfer_type = emi_2_per, + .event_id = DMA_REQ_ASRC_DMA3, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_ASRCC_RX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_asrcc_tx_params = { + .chnl_params = { + .watermark_level = MXC_ASRC_FIFO_WML * 3, + .per_address = ASRC_BASE_ADDR + MXC_ASRCC_TX_REG, + .peripheral_type = ASRC, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_ASRC_DMA6, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_ASRCC_TX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_ext_params_t mxc_sdma_asrca_ssi1_tx0_params = { + .chnl_ext_params = { + .common = { + .watermark_level = + MXC_ASRC_FIFO_WML >> 1, + .per_address = + SSI1_BASE_ADDR + MXC_SSI_TX0_REG, + .peripheral_type = ASRC, + .transfer_type = per_2_per, + .event_id = DMA_REQ_SSI1_TX1, + .event_id2 = DMA_REQ_ASRC_DMA4, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + .ext = 1, + }, + .p2p_dir = 0, + .info_bits = + SDMA_ASRC_P2P_INFO_CONT | SDMA_ASRC_P2P_INFO_SP, + .watermark_level2 = MXC_SSI_TXFIFO_WML, + .per_address2 = ASRC_BASE_ADDR + MXC_ASRCA_TX_REG, + }, + .channel_num = MXC_DMA_CHANNEL_ASRCA_SSI1_TX0, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_ext_params_t mxc_sdma_asrca_ssi1_tx1_params = { + .chnl_ext_params = { + .common = { + .watermark_level = + MXC_ASRC_FIFO_WML >> 1, + .per_address = + SSI1_BASE_ADDR + MXC_SSI_TX1_REG, + .peripheral_type = ASRC, + .transfer_type = per_2_per, + .event_id = DMA_REQ_SSI1_TX2, + .event_id2 = DMA_REQ_ASRC_DMA4, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + .ext = 1, + }, + .p2p_dir = 0, + .info_bits = + SDMA_ASRC_P2P_INFO_CONT | SDMA_ASRC_P2P_INFO_SP, + .watermark_level2 = MXC_SSI_TXFIFO_WML, + .per_address2 = ASRC_BASE_ADDR + MXC_ASRCA_TX_REG, + }, + .channel_num = MXC_DMA_CHANNEL_ASRCA_SSI1_TX1, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_ext_params_t mxc_sdma_asrca_ssi2_tx0_params = { + .chnl_ext_params = { + .common = { + .watermark_level = + MXC_ASRC_FIFO_WML >> 1, + .per_address = + SSI2_BASE_ADDR + MXC_SSI_TX0_REG, + .peripheral_type = ASRC, + .transfer_type = per_2_per, + .event_id = DMA_REQ_SSI2_TX1, + .event_id2 = DMA_REQ_ASRC_DMA4, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + .ext = 1, + }, + .p2p_dir = 0, + .info_bits = + SDMA_ASRC_P2P_INFO_CONT | SDMA_ASRC_P2P_INFO_SP | + SDMA_ASRC_P2P_INFO_DP, + .watermark_level2 = MXC_SSI_TXFIFO_WML, + .per_address2 = ASRC_BASE_ADDR + MXC_ASRCA_TX_REG, + }, + .channel_num = MXC_DMA_CHANNEL_ASRCA_SSI2_TX0, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_ext_params_t mxc_sdma_asrca_ssi2_tx1_params = { + .chnl_ext_params = { + .common = { + .watermark_level = + MXC_ASRC_FIFO_WML >> 1, + .per_address = + SSI2_BASE_ADDR + MXC_SSI_TX1_REG, + .peripheral_type = ASRC, + .transfer_type = per_2_per, + .event_id = DMA_REQ_SSI2_TX2, + .event_id2 = DMA_REQ_ASRC_DMA4, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + .ext = 1, + }, + .p2p_dir = 0, + .info_bits = + SDMA_ASRC_P2P_INFO_CONT | SDMA_ASRC_P2P_INFO_SP | + SDMA_ASRC_P2P_INFO_DP, + .watermark_level2 = MXC_SSI_TXFIFO_WML, + .per_address2 = ASRC_BASE_ADDR + MXC_ASRCA_TX_REG, + }, + .channel_num = MXC_DMA_CHANNEL_ASRCA_SSI2_TX1, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_ext_params_t mxc_sdma_asrcb_ssi1_tx0_params = { + .chnl_ext_params = { + .common = { + .watermark_level = + MXC_ASRC_FIFO_WML >> 1, + .per_address = + SSI1_BASE_ADDR + MXC_SSI_TX0_REG, + .peripheral_type = ASRC, + .transfer_type = per_2_per, + .event_id = DMA_REQ_SSI1_TX1, + .event_id2 = DMA_REQ_ASRC_DMA5, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + .ext = 1, + }, + .p2p_dir = 0, + .info_bits = + SDMA_ASRC_P2P_INFO_CONT | SDMA_ASRC_P2P_INFO_SP, + .watermark_level2 = MXC_SSI_TXFIFO_WML, + .per_address2 = ASRC_BASE_ADDR + MXC_ASRCB_TX_REG, + }, + .channel_num = MXC_DMA_CHANNEL_ASRCB_SSI1_TX0, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_ext_params_t mxc_sdma_asrcb_ssi1_tx1_params = { + .chnl_ext_params = { + .common = { + .watermark_level = + MXC_ASRC_FIFO_WML >> 1, + .per_address = + SSI1_BASE_ADDR + MXC_SSI_TX1_REG, + .peripheral_type = ASRC, + .transfer_type = per_2_per, + .event_id = DMA_REQ_SSI1_TX2, + .event_id2 = DMA_REQ_ASRC_DMA5, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + .ext = 1, + }, + .p2p_dir = 0, + .info_bits = + SDMA_ASRC_P2P_INFO_CONT | SDMA_ASRC_P2P_INFO_SP, + .watermark_level2 = MXC_SSI_TXFIFO_WML, + .per_address2 = ASRC_BASE_ADDR + MXC_ASRCB_TX_REG, + }, + .channel_num = MXC_DMA_CHANNEL_ASRCB_SSI1_TX1, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_ext_params_t mxc_sdma_asrcb_ssi2_tx0_params = { + .chnl_ext_params = { + .common = { + .watermark_level = + MXC_ASRC_FIFO_WML >> 1, + .per_address = + SSI2_BASE_ADDR + MXC_SSI_TX0_REG, + .peripheral_type = ASRC, + .transfer_type = per_2_per, + .event_id = DMA_REQ_SSI2_TX1, + .event_id2 = DMA_REQ_ASRC_DMA5, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + .ext = 1, + }, + .p2p_dir = 0, + .info_bits = + SDMA_ASRC_P2P_INFO_CONT | SDMA_ASRC_P2P_INFO_SP | + SDMA_ASRC_P2P_INFO_DP, + .watermark_level2 = MXC_SSI_TXFIFO_WML, + .per_address2 = ASRC_BASE_ADDR + MXC_ASRCB_TX_REG, + }, + .channel_num = MXC_DMA_CHANNEL_ASRCB_SSI2_TX0, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_ext_params_t mxc_sdma_asrcb_ssi2_tx1_params = { + .chnl_ext_params = { + .common = { + .watermark_level = + MXC_ASRC_FIFO_WML >> 1, + .per_address = + SSI2_BASE_ADDR + MXC_SSI_TX1_REG, + .peripheral_type = ASRC, + .transfer_type = per_2_per, + .event_id = DMA_REQ_SSI2_TX2, + .event_id2 = DMA_REQ_ASRC_DMA5, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + .ext = 1, + }, + .p2p_dir = 0, + .info_bits = + SDMA_ASRC_P2P_INFO_CONT | SDMA_ASRC_P2P_INFO_SP | + SDMA_ASRC_P2P_INFO_DP, + .watermark_level2 = MXC_SSI_TXFIFO_WML, + .per_address2 = ASRC_BASE_ADDR + MXC_ASRCB_TX_REG, + }, + .channel_num = MXC_DMA_CHANNEL_ASRCB_SSI2_TX1, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_ext_params_t mxc_sdma_asrca_esai_params = { + .chnl_ext_params = { + .common = { + .watermark_level = + MXC_ASRC_FIFO_WML >> 1, + .per_address = + ESAI_BASE_ADDR + MXC_ESAI_TX_REG, + .peripheral_type = ASRC, + .transfer_type = per_2_per, + .event_id = DMA_REQ_ESAI_TX, + .event_id2 = DMA_REQ_ASRC_DMA4, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + .ext = 1, + }, + .p2p_dir = 0, + .info_bits = + SDMA_ASRC_P2P_INFO_CONT | SDMA_ASRC_P2P_INFO_SP | + SDMA_ASRC_P2P_INFO_DP, + .watermark_level2 = MXC_ESAI_FIFO_WML, + .per_address2 = ASRC_BASE_ADDR + MXC_ASRCA_TX_REG, + }, + .channel_num = MXC_DMA_CHANNEL_ASRCA_ESAI, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_ext_params_t mxc_sdma_asrcb_esai_params = { + .chnl_ext_params = { + .common = { + .watermark_level = + MXC_ASRC_FIFO_WML >> 1, + .per_address = + ESAI_BASE_ADDR + MXC_ESAI_TX_REG, + .peripheral_type = ASRC, + .transfer_type = per_2_per, + .event_id = DMA_REQ_ESAI_TX, + .event_id2 = DMA_REQ_ASRC_DMA5, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + .ext = 1, + }, + .p2p_dir = 0, + .info_bits = + SDMA_ASRC_P2P_INFO_CONT | SDMA_ASRC_P2P_INFO_SP | + SDMA_ASRC_P2P_INFO_DP, + .watermark_level2 = MXC_ESAI_FIFO_WML, + .per_address2 = ASRC_BASE_ADDR + MXC_ASRCB_TX_REG, + }, + .channel_num = MXC_DMA_CHANNEL_ASRCB_ESAI, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_ext_params_t mxc_sdma_asrcc_esai_params = { + .chnl_ext_params = { + .common = { + .watermark_level = + MXC_ASRC_FIFO_WML >> 1, + .per_address = + ESAI_BASE_ADDR + MXC_ESAI_TX_REG, + .peripheral_type = ASRC, + .transfer_type = per_2_per, + .event_id = DMA_REQ_ESAI_TX, + .event_id2 = DMA_REQ_ASRC_DMA6, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + .ext = 1, + }, + .p2p_dir = 0, + .info_bits = + SDMA_ASRC_P2P_INFO_CONT | SDMA_ASRC_P2P_INFO_SP | + SDMA_ASRC_P2P_INFO_DP, + .watermark_level2 = MXC_ASRC_FIFO_WML, + .per_address2 = ASRC_BASE_ADDR + MXC_ASRCC_TX_REG, + }, + .channel_num = MXC_DMA_CHANNEL_ASRCC_ESAI, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_esai_16bit_rx_params = { + .chnl_params = { + .watermark_level = MXC_ESAI_FIFO_WML, + .per_address = ESAI_BASE_ADDR + MXC_ESAI_RX_REG, + .peripheral_type = ESAI, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_ESAI_RX, + .bd_number = 32, + .word_size = TRANSFER_16BIT, + }, + .channel_num = MXC_DMA_CHANNEL_ESAI_RX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_esai_16bit_tx_params = { + .chnl_params = { + .watermark_level = MXC_ESAI_FIFO_WML, + .per_address = ESAI_BASE_ADDR + MXC_ESAI_TX_REG, + .peripheral_type = ESAI, + .transfer_type = int_2_per, + .event_id = DMA_REQ_ESAI_TX, + .bd_number = 32, + .word_size = TRANSFER_16BIT, + }, + .channel_num = MXC_DMA_CHANNEL_ESAI_TX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_esai_24bit_rx_params = { + .chnl_params = { + .watermark_level = MXC_ESAI_FIFO_WML, + .per_address = ESAI_BASE_ADDR + MXC_ESAI_RX_REG, + .peripheral_type = ESAI, + .transfer_type = per_2_emi, + .event_id = DMA_REQ_ESAI_RX, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_ESAI_RX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + +static mxc_sdma_channel_params_t mxc_sdma_esai_24bit_tx_params = { + .chnl_params = { + .watermark_level = MXC_ESAI_FIFO_WML, + .per_address = ESAI_BASE_ADDR + MXC_ESAI_TX_REG, + .peripheral_type = ESAI, + .transfer_type = int_2_per, + .event_id = DMA_REQ_ESAI_TX, + .bd_number = 32, + .word_size = TRANSFER_32BIT, + }, + .channel_num = MXC_DMA_CHANNEL_ESAI_TX, + .chnl_priority = MXC_SDMA_DEFAULT_PRIORITY, +}; + static mxc_sdma_info_entry_t mxc_sdma_active_dma_info[] = { {MXC_DMA_UART1_RX, &mxc_sdma_uart1_rx_params}, {MXC_DMA_UART1_TX, &mxc_sdma_uart1_tx_params}, @@ -590,6 +1096,10 @@ static mxc_sdma_info_entry_t mxc_sdma_active_dma_info[] = { {MXC_DMA_UART2_TX, &mxc_sdma_uart2_tx_params}, {MXC_DMA_UART3_RX, &mxc_sdma_uart3_rx_params}, {MXC_DMA_UART3_TX, &mxc_sdma_uart3_tx_params}, + {MXC_DMA_UART4_RX, &mxc_sdma_uart4_rx_params}, + {MXC_DMA_UART4_TX, &mxc_sdma_uart4_tx_params}, + {MXC_DMA_UART5_RX, &mxc_sdma_uart5_rx_params}, + {MXC_DMA_UART5_TX, &mxc_sdma_uart5_tx_params}, {MXC_DMA_MMC1_WIDTH_1, &mxc_sdma_mmc1_width1_params}, {MXC_DMA_MMC1_WIDTH_4, &mxc_sdma_mmc1_width4_params}, {MXC_DMA_MMC2_WIDTH_1, &mxc_sdma_mmc2_width1_params}, @@ -623,11 +1133,60 @@ static mxc_sdma_info_entry_t mxc_sdma_active_dma_info[] = { {MXC_DMA_ATA_TX, &mxc_sdma_ata_tx_params}, {MXC_DMA_SPDIF_16BIT_TX, &mxc_sdma_spdif_16bit_tx_params}, {MXC_DMA_SPDIF_32BIT_TX, &mxc_sdma_spdif_32bit_tx_params}, + {MXC_DMA_SPDIF_32BIT_RX, &mxc_sdma_spdif_32bit_rx_params}, + {MXC_DMA_ASRC_A_RX, &mxc_sdma_asrca_rx_params}, + {MXC_DMA_ASRC_A_TX, &mxc_sdma_asrca_tx_params}, + {MXC_DMA_ASRC_B_RX, &mxc_sdma_asrcb_rx_params}, + {MXC_DMA_ASRC_B_TX, &mxc_sdma_asrcb_tx_params}, + {MXC_DMA_ASRC_C_RX, &mxc_sdma_asrcc_rx_params}, + {MXC_DMA_ASRC_C_TX, &mxc_sdma_asrcc_tx_params}, + {MXC_DMA_ASRCA_SSI1_TX0, &mxc_sdma_asrca_ssi1_tx0_params}, + {MXC_DMA_ASRCA_SSI1_TX1, &mxc_sdma_asrca_ssi1_tx1_params}, + {MXC_DMA_ASRCA_SSI2_TX0, &mxc_sdma_asrca_ssi2_tx0_params}, + {MXC_DMA_ASRCA_SSI2_TX1, &mxc_sdma_asrca_ssi2_tx1_params}, + {MXC_DMA_ASRCB_SSI1_TX0, &mxc_sdma_asrcb_ssi1_tx0_params}, + {MXC_DMA_ASRCB_SSI1_TX1, &mxc_sdma_asrcb_ssi1_tx1_params}, + {MXC_DMA_ASRCB_SSI2_TX0, &mxc_sdma_asrcb_ssi2_tx0_params}, + {MXC_DMA_ASRCB_SSI2_TX1, &mxc_sdma_asrcb_ssi2_tx1_params}, + {MXC_DMA_ASRCA_ESAI, &mxc_sdma_asrca_esai_params}, + {MXC_DMA_ASRCB_ESAI, &mxc_sdma_asrcb_esai_params}, + {MXC_DMA_ASRCC_ESAI, &mxc_sdma_asrcc_esai_params}, + {MXC_DMA_ESAI_16BIT_RX, &mxc_sdma_esai_16bit_rx_params}, + {MXC_DMA_ESAI_16BIT_TX, &mxc_sdma_esai_16bit_tx_params}, + {MXC_DMA_ESAI_24BIT_RX, &mxc_sdma_esai_24bit_rx_params}, + {MXC_DMA_ESAI_24BIT_TX, &mxc_sdma_esai_24bit_tx_params}, }; static int mxc_sdma_info_entrys = sizeof(mxc_sdma_active_dma_info) / sizeof(mxc_sdma_active_dma_info[0]); +static int __init dma_fixups(void) +{ + mxc_sdma_info_entry_t *p = mxc_sdma_active_dma_info; + int i; + dma_channel_ext_params *params; + + if (cpu_is_mx51()) + return 0; + + for (i = 0; i < mxc_sdma_info_entrys; i++, p++) { + params = &(((mxc_sdma_channel_ext_params_t *)p->chnl_info)->chnl_ext_params); + params->common.per_address -= 0x20000000; + if (params->common.ext) + params->per_address2 -= 0x20000000; + } + + mxc_sdma_uart2_rx_params.chnl_params.event_id = DMA_REQ_FIRI_RX; + mxc_sdma_uart2_tx_params.chnl_params.event_id = DMA_REQ_FIRI_TX; + mxc_sdma_uart3_rx_params.chnl_params.event_id = DMA_REQ_UART3_RX_MX53; + mxc_sdma_uart3_tx_params.chnl_params.event_id = DMA_REQ_UART3_TX_MX53; + mxc_sdma_spdif_16bit_tx_params.chnl_params.event_id = DMA_REQ_SPDIF_TX; + mxc_sdma_spdif_32bit_tx_params.chnl_params.event_id = DMA_REQ_SPDIF_TX; + + return 0; +} +arch_initcall(dma_fixups); + /*! * This functions Returns the SDMA paramaters associated for a module * @@ -647,6 +1206,7 @@ mxc_sdma_channel_params_t *mxc_sdma_get_channel_params(mxc_dma_device_t } return NULL; } +EXPORT_SYMBOL(mxc_sdma_get_channel_params); /*! * This functions marks the SDMA channels that are statically allocated @@ -661,6 +1221,139 @@ void mxc_get_static_channels(mxc_dma_channel_t *chnl) chnl[i].dynamic = 0; #endif } - -EXPORT_SYMBOL(mxc_sdma_get_channel_params); EXPORT_SYMBOL(mxc_get_static_channels); + +static void __init mx51_sdma_get_script_info(sdma_script_start_addrs *sdma_script_addr) +{ + /* AP<->BP */ + sdma_script_addr->mxc_sdma_ap_2_ap_addr = ap_2_ap_ADDR; + sdma_script_addr->mxc_sdma_ap_2_bp_addr = -1; + sdma_script_addr->mxc_sdma_bp_2_ap_addr = -1; + sdma_script_addr->mxc_sdma_ap_2_ap_fixed_addr = -1; + + /*misc */ + sdma_script_addr->mxc_sdma_loopback_on_dsp_side_addr = -1; + sdma_script_addr->mxc_sdma_mcu_interrupt_only_addr = -1; + + /* firi */ + sdma_script_addr->mxc_sdma_firi_2_per_addr = -1; + sdma_script_addr->mxc_sdma_firi_2_mcu_addr = -1; + sdma_script_addr->mxc_sdma_per_2_firi_addr = -1; + sdma_script_addr->mxc_sdma_mcu_2_firi_addr = -1; + + /* uart */ + sdma_script_addr->mxc_sdma_uart_2_per_addr = uart_2_per_ADDR; + sdma_script_addr->mxc_sdma_uart_2_mcu_addr = uart_2_mcu_ADDR; + + /* UART SH */ + sdma_script_addr->mxc_sdma_uartsh_2_per_addr = uartsh_2_per_ADDR; + sdma_script_addr->mxc_sdma_uartsh_2_mcu_addr = uartsh_2_mcu_ADDR; + + /* SHP */ + sdma_script_addr->mxc_sdma_per_2_shp_addr = per_2_shp_ADDR; + sdma_script_addr->mxc_sdma_shp_2_per_addr = shp_2_per_ADDR; + sdma_script_addr->mxc_sdma_mcu_2_shp_addr = mcu_2_shp_ADDR; + sdma_script_addr->mxc_sdma_shp_2_mcu_addr = shp_2_mcu_ADDR; + + /* ATA */ + sdma_script_addr->mxc_sdma_mcu_2_ata_addr = mcu_2_ata_ADDR; + sdma_script_addr->mxc_sdma_ata_2_mcu_addr = ata_2_mcu_ADDR; + + /* app */ + sdma_script_addr->mxc_sdma_app_2_per_addr = app_2_per_ADDR; + sdma_script_addr->mxc_sdma_app_2_mcu_addr = app_2_mcu_ADDR; + sdma_script_addr->mxc_sdma_per_2_app_addr = per_2_app_ADDR; + sdma_script_addr->mxc_sdma_mcu_2_app_addr = mcu_2_app_ADDR; + + /* MSHC */ + sdma_script_addr->mxc_sdma_mshc_2_mcu_addr = -1; + sdma_script_addr->mxc_sdma_mcu_2_mshc_addr = -1; + + /* spdif */ + sdma_script_addr->mxc_sdma_spdif_2_mcu_addr = -1; + sdma_script_addr->mxc_sdma_mcu_2_spdif_addr = mcu_2_spdif_ADDR; + + /* IPU */ + sdma_script_addr->mxc_sdma_ext_mem_2_ipu_addr = ext_mem__ipu_ram_ADDR; + + /* DVFS */ + sdma_script_addr->mxc_sdma_dptc_dvfs_addr = -1; + + /* core */ + sdma_script_addr->mxc_sdma_start_addr = (unsigned short *)sdma_code; + sdma_script_addr->mxc_sdma_ram_code_start_addr = RAM_CODE_START_ADDR; + sdma_script_addr->mxc_sdma_ram_code_size = RAM_CODE_SIZE; +} + +static void __init mx53_sdma_get_script_info(sdma_script_start_addrs *sdma_script_addr) +{ + /* AP<->BP */ + sdma_script_addr->mxc_sdma_ap_2_ap_addr = ap_2_ap_ADDR_MX53; + sdma_script_addr->mxc_sdma_ap_2_bp_addr = -1; + sdma_script_addr->mxc_sdma_bp_2_ap_addr = -1; + sdma_script_addr->mxc_sdma_ap_2_ap_fixed_addr = -1; + + /*misc */ + sdma_script_addr->mxc_sdma_loopback_on_dsp_side_addr = -1; + sdma_script_addr->mxc_sdma_mcu_interrupt_only_addr = -1; + + /* firi */ + sdma_script_addr->mxc_sdma_firi_2_per_addr = firi_2_mcu_ADDR_MX53; + sdma_script_addr->mxc_sdma_firi_2_mcu_addr = firi_2_mcu_ADDR_MX53; + sdma_script_addr->mxc_sdma_per_2_firi_addr = mcu_2_firi_ADDR_MX53; + sdma_script_addr->mxc_sdma_mcu_2_firi_addr = mcu_2_firi_ADDR_MX53; + + /* uart */ + sdma_script_addr->mxc_sdma_uart_2_per_addr = uart_2_mcu_ADDR_MX53; + sdma_script_addr->mxc_sdma_uart_2_mcu_addr = uart_2_mcu_ADDR_MX53; + + /* UART SH */ + sdma_script_addr->mxc_sdma_uartsh_2_per_addr = uartsh_2_mcu_ADDR_MX53; + sdma_script_addr->mxc_sdma_uartsh_2_mcu_addr = uartsh_2_mcu_ADDR_MX53; + + /* SHP */ + sdma_script_addr->mxc_sdma_per_2_shp_addr = mcu_2_shp_ADDR_MX53; + sdma_script_addr->mxc_sdma_shp_2_per_addr = shp_2_mcu_ADDR_MX53; + sdma_script_addr->mxc_sdma_mcu_2_shp_addr = mcu_2_shp_ADDR_MX53; + sdma_script_addr->mxc_sdma_shp_2_mcu_addr = shp_2_mcu_ADDR_MX53; + + /* ATA use it's own DMA */ + sdma_script_addr->mxc_sdma_mcu_2_ata_addr = -1; + sdma_script_addr->mxc_sdma_ata_2_mcu_addr = -1; + + /* app */ + sdma_script_addr->mxc_sdma_app_2_per_addr = app_2_mcu_ADDR_MX53; + sdma_script_addr->mxc_sdma_app_2_mcu_addr = app_2_mcu_ADDR_MX53; + sdma_script_addr->mxc_sdma_per_2_app_addr = mcu_2_app_ADDR_MX53; + sdma_script_addr->mxc_sdma_mcu_2_app_addr = mcu_2_app_ADDR_MX53; + + /* MSHC */ + sdma_script_addr->mxc_sdma_mshc_2_mcu_addr = -1; + sdma_script_addr->mxc_sdma_mcu_2_mshc_addr = -1; + + /* spdif */ + sdma_script_addr->mxc_sdma_spdif_2_mcu_addr = spdif_2_mcu_ADDR_MX53; + sdma_script_addr->mxc_sdma_mcu_2_spdif_addr = mcu_2_spdif_ADDR_MX53; + + sdma_script_addr->mxc_sdma_asrc_2_mcu_addr = asrc__mcu_ADDR_MX53; + + /* IPU */ + sdma_script_addr->mxc_sdma_ext_mem_2_ipu_addr = mcu_2_app_ADDR_MX53; + + /* DVFS */ + sdma_script_addr->mxc_sdma_dptc_dvfs_addr = -1; + + /* core */ + sdma_script_addr->mxc_sdma_start_addr = (unsigned short *)sdma_code; + sdma_script_addr->mxc_sdma_ram_code_start_addr = RAM_CODE_START_ADDR_MX53; + sdma_script_addr->mxc_sdma_ram_code_size = RAM_CODE_SIZE_MX53; +} + +void __init mxc_sdma_get_script_info(sdma_script_start_addrs *sdma_script_addr) +{ + if (cpu_is_mx51()) + mx51_sdma_get_script_info(sdma_script_addr); + else + mx53_sdma_get_script_info(sdma_script_addr); +} + diff --git a/arch/arm/mach-mx5/iomux.c b/arch/arm/mach-mx5/iomux.c index 3af813347118..2d01d8b55570 100644 --- a/arch/arm/mach-mx5/iomux.c +++ b/arch/arm/mach-mx5/iomux.c @@ -1,5 +1,5 @@ /* - * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. */ /* @@ -12,15 +12,15 @@ */ /*! - * @defgroup GPIO_MX51 Board GPIO and Muxing Setup - * @ingroup MSL_MX51 + * @defgroup GPIO_MX5 Board GPIO and Muxing Setup + * @ingroup MSL_MX5 */ /*! - * @file mach-mx51/iomux.c + * @file mach-mx5/iomux.c * * @brief I/O Muxing control functions * - * @ingroup GPIO_MX51 + * @ingroup GPIO_MX5 */ #include <linux/io.h> @@ -30,22 +30,32 @@ #include <mach/gpio.h> #include <mach/irqs.h> #include "iomux.h" +#include "mx51_pins.h" + +#define MUX_I_START_MX53 0x0020 +#define PAD_I_START_MX53 0x348 +#define INPUT_CTL_START_MX53 0x730 +#define MUX_I_END_MX53 (PAD_I_START_MX53 - 4) /*! - * IOMUX register (base) addresses + * IOMUX register (base) addressesf */ #define IOMUXGPR0 (IO_ADDRESS(IOMUXC_BASE_ADDR)) #define IOMUXGPR1 (IO_ADDRESS(IOMUXC_BASE_ADDR) + 0x004) #define IOMUXSW_MUX_CTL (IO_ADDRESS(IOMUXC_BASE_ADDR)) -#define IOMUXSW_MUX_END (IO_ADDRESS(IOMUXC_BASE_ADDR) + MUX_I_END) -#define IOMUXSW_PAD_CTL (IO_ADDRESS(IOMUXC_BASE_ADDR) + PAD_I_START) #define IOMUXSW_INPUT_CTL (IO_ADDRESS(IOMUXC_BASE_ADDR)) -#define MUX_PIN_NUM_MAX ((MUX_I_END >> 2) + 1) - -static u8 iomux_pin_res_table[MUX_PIN_NUM_MAX]; +static u8 iomux_pin_res_table[(0x3F0 / 4) + 1]; static DEFINE_SPINLOCK(gpio_mux_lock); +static inline void *_get_sw_pad(void) +{ + if (cpu_is_mx51()) + return IO_ADDRESS(IOMUXC_BASE_ADDR) + PAD_I_START_MX51; + else + return IO_ADDRESS(IOMUXC_BASE_ADDR) + PAD_I_START_MX53; +} + static inline void * _get_mux_reg(iomux_pin_name_t pin) { u32 mux_reg = PIN_TO_IOMUX_MUX(pin); @@ -66,26 +76,28 @@ static inline void * _get_mux_reg(iomux_pin_name_t pin) static inline void * _get_pad_reg(iomux_pin_name_t pin) { u32 pad_reg = PIN_TO_IOMUX_PAD(pin); + void __iomem *sw_pad_reg = _get_sw_pad(); + if (cpu_is_mx51_rev(CHIP_REV_2_0) < 0) { if ((pin == MX51_PIN_NANDF_RB5) || (pin == MX51_PIN_NANDF_RB6) || (pin == MX51_PIN_NANDF_RB7)) ; /* Do nothing */ - else if (pad_reg == 0x4D0 - PAD_I_START) + else if (pad_reg == 0x4D0 - PAD_I_START_MX51) pad_reg += 0x4C; - else if (pad_reg == 0x860 - PAD_I_START) + else if (pad_reg == 0x860 - PAD_I_START_MX51) pad_reg += 0x9C; - else if (pad_reg >= 0x804 - PAD_I_START) + else if (pad_reg >= 0x804 - PAD_I_START_MX51) pad_reg += 0xB0; - else if (pad_reg >= 0x7FC - PAD_I_START) + else if (pad_reg >= 0x7FC - PAD_I_START_MX51) pad_reg += 0xB4; - else if (pad_reg >= 0x4E4 - PAD_I_START) + else if (pad_reg >= 0x4E4 - PAD_I_START_MX51) pad_reg += 0xCC; else pad_reg += 8; } - return IOMUXSW_PAD_CTL + pad_reg; + return sw_pad_reg + pad_reg; } static inline void * _get_mux_end(void) @@ -193,8 +205,9 @@ EXPORT_SYMBOL(mxc_free_iomux); void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config) { void __iomem *pad_reg = _get_pad_reg(pin); + void __iomem *sw_pad_reg = _get_sw_pad(); - BUG_ON(pad_reg < IOMUXSW_PAD_CTL); + BUG_ON(pad_reg < sw_pad_reg); __raw_writel(config, pad_reg); } EXPORT_SYMBOL(mxc_iomux_set_pad); @@ -233,10 +246,11 @@ void mxc_iomux_set_input(iomux_input_select_t input, u32 config) else if (input >= MUX_IN_CCM_PLL1_BYPASS_CLK_SELECT_INPUT) input -= 1; - reg = IOMUXSW_INPUT_CTL + (input << 2) + INPUT_CTL_START_TO1; - } else { - reg = IOMUXSW_INPUT_CTL + (input << 2) + INPUT_CTL_START; - } + reg = IOMUXSW_INPUT_CTL + (input << 2) + INPUT_CTL_START_MX51_TO1; + } else if (cpu_is_mx51()) { + reg = IOMUXSW_INPUT_CTL + (input << 2) + INPUT_CTL_START_MX51; + } else + reg = IOMUXSW_INPUT_CTL + (input << 2) + INPUT_CTL_START_MX53; BUG_ON(input >= MUX_INPUT_NUM_MUX); __raw_writel(config, reg); diff --git a/arch/arm/mach-mx5/iomux.h b/arch/arm/mach-mx5/iomux.h index e314ab26ac9b..0732f2169e0a 100644 --- a/arch/arm/mach-mx5/iomux.h +++ b/arch/arm/mach-mx5/iomux.h @@ -1,5 +1,5 @@ /* - * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. */ /* @@ -10,22 +10,80 @@ * http://www.opensource.org/licenses/gpl-license.html * http://www.gnu.org/copyleft/gpl.html */ -#ifndef __MACH_MX51_IOMUX_H__ -#define __MACH_MX51_IOMUX_H__ +#ifndef __MACH_MX5_IOMUX_H__ +#define __MACH_MX5_IOMUX_H__ #include <linux/types.h> #include <mach/gpio.h> -#include "mx51_pins.h" /*! - * @file mach-mx51/iomux.h + * @file mach-mx5/iomux.h * * @brief I/O Muxing control definitions and functions * - * @ingroup GPIO_MX51 + * @ingroup GPIO_MX5 */ +/*! + * @name IOMUX/PAD Bit field definitions + */ + +/*! @{ */ + +/*! + * In order to identify pins more effectively, each mux-controlled pin's + * enumerated value is constructed in the following way: + * + * ------------------------------------------------------------------- + * 31-29 | 28 - 24 | 23 - 21 | 20 - 10| 9 - 0 + * ------------------------------------------------------------------- + * IO_P | IO_I | GPIO_I | PAD_I | MUX_I + * ------------------------------------------------------------------- + * + * Bit 0 to 9 contains MUX_I used to identify the register + * offset (0-based. base is IOMUX_module_base) defined in the Section + * "sw_pad_ctl & sw_mux_ctl details" of the IC Spec. The + * similar field definitions are used for the pad control register. + * For example, the MX51_PIN_ETM_D0 is defined in the enumeration: + * ( (0x28 - MUX_I_START) << MUX_I)|( (0x250 - PAD_I_START) << PAD_I) + * It means the mux control register is at register offset 0x28. The pad control + * register offset is: 0x250 and also occupy the least significant bits + * within the register. + */ + +/*! + * Starting bit position within each entry of \b iomux_pins to represent the + * MUX control register offset + */ +#define MUX_I 0 +/*! + * Starting bit position within each entry of \b iomux_pins to represent the + * PAD control register offset + */ +#define PAD_I 10 +/*! + * Starting bit position within each entry of \b iomux_pins to represent which + * mux mode is for GPIO (0-based) + */ +#define GPIO_I 21 + +#define NON_GPIO_PORT 0x7 +#define PIN_TO_MUX_MASK ((1 << (PAD_I - MUX_I)) - 1) +#define PIN_TO_PAD_MASK ((1 << (GPIO_I - PAD_I)) - 1) +#define PIN_TO_ALT_GPIO_MASK ((1 << (MUX_IO_I - GPIO_I)) - 1) + +#define NON_MUX_I PIN_TO_MUX_MASK +#define NON_PAD_I PIN_TO_PAD_MASK + +#define PIN_TO_IOMUX_MUX(pin) ((pin >> MUX_I) & PIN_TO_MUX_MASK) +#define PIN_TO_IOMUX_PAD(pin) ((pin >> PAD_I) & PIN_TO_PAD_MASK) +#define PIN_TO_ALT_GPIO(pin) ((pin >> GPIO_I) & PIN_TO_ALT_GPIO_MASK) +#define PIN_TO_IOMUX_INDEX(pin) (PIN_TO_IOMUX_MUX(pin) >> 2) + +/*! @} End IOMUX/PAD Bit field definitions */ + typedef unsigned int iomux_pin_name_t; +typedef unsigned int iomux_input_select_t; /*! * various IOMUX output functions @@ -56,7 +114,9 @@ typedef enum iomux_pad_config { PAD_CTL_ODE_OPENDRAIN_NONE = 0x0 << 3, PAD_CTL_ODE_OPENDRAIN_ENABLE = 0x1 << 3, PAD_CTL_100K_PD = 0x0 << 4, + PAD_CTL_360K_PD = 0x0 << 4, PAD_CTL_47K_PU = 0x1 << 4, + PAD_CTL_75k_PU = 0x1 << 4, PAD_CTL_100K_PU = 0x2 << 4, PAD_CTL_22K_PU = 0x3 << 4, PAD_CTL_PUE_KEEPER = 0x0 << 6, @@ -72,110 +132,6 @@ typedef enum iomux_pad_config { } iomux_pad_config_t; /*! - * various IOMUX input select register index - */ -typedef enum iomux_input_select { - MUX_IN_AUDMUX_P4_INPUT_DA_AMX_SELECT_I = 0, - MUX_IN_AUDMUX_P4_INPUT_DB_AMX_SELECT_I, - MUX_IN_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT, - MUX_IN_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT, - MUX_IN_AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT, - MUX_IN_AUDMUX_P5_INPUT_DB_AMX_SELECT_INPUT, - MUX_IN_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT, - MUX_IN_AUDMUX_P5_INPUT_RXFS_AMX_SELECT, - MUX_IN_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT, - MUX_IN_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT, - MUX_IN_AUDMUX_P6_INPUT_DA_AMX_SELECT_INPUT, - MUX_IN_AUDMUX_P6_INPUT_DB_AMX_SELECT_INPUT, - MUX_IN_AUDMUX_P6_INPUT_RXCLK_AMX_SELECT_INPUT, - MUX_IN_AUDMUX_P6_INPUT_RXFS_AMX_SELECT_INPUT, - MUX_IN_AUDMUX_P6_INPUT_TXCLK_AMX_SELECT_INPUT, - MUX_IN_AUDMUX_P6_INPUT_TXFS_AMX_SELECT_INPUT, - MUX_IN_CCM_IPP_DI_CLK_SELECT_INPUT, - /* TO2 */ - MUX_IN_CCM_IPP_DI1_CLK_SELECT_INPUT, - MUX_IN_CCM_PLL1_BYPASS_CLK_SELECT_INPUT, - MUX_IN_CCM_PLL2_BYPASS_CLK_SELECT_INPUT, - MUX_IN_CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT, - MUX_IN_CSPI_IPP_IND_MISO_SELECT_INPUT, - MUX_IN_CSPI_IPP_IND_MOSI_SELECT_INPUT, - MUX_IN_CSPI_IPP_IND_SS_B_1_SELECT_INPUT, - MUX_IN_CSPI_IPP_IND_SS_B_2_SELECT_INPUT, - MUX_IN_CSPI_IPP_IND_SS_B_3_SELECT_INPUT, - MUX_IN_DPLLIP1_L1T_TOG_EN_SELECT_INPUT, - /* TO2 */ - MUX_IN_ECSPI2_IPP_IND_SS_B_1_SELECT_INPUT, - MUX_IN_ECSPI2_IPP_IND_SS_B_3_SELECT_INPUT, - MUX_IN_EMI_IPP_IND_RDY_INT_SELECT_INPUT, - MUX_IN_ESDHC3_IPP_DAT0_IN_SELECT_INPUT, - MUX_IN_ESDHC3_IPP_DAT1_IN_SELECT_INPUT, - MUX_IN_ESDHC3_IPP_DAT2_IN_SELECT_INPUT, - MUX_IN_ESDHC3_IPP_DAT3_IN_SELECT_INPUT, - MUX_IN_FEC_FEC_COL_SELECT_INPUT, - MUX_IN_FEC_FEC_CRS_SELECT_INPUT, - MUX_IN_FEC_FEC_MDI_SELECT_INPUT, - MUX_IN_FEC_FEC_RDATA_0_SELECT_INPUT, - MUX_IN_FEC_FEC_RDATA_1_SELECT_INPUT, - MUX_IN_FEC_FEC_RDATA_2_SELECT_INPUT, - MUX_IN_FEC_FEC_RDATA_3_SELECT_INPUT, - MUX_IN_FEC_FEC_RX_CLK_SELECT_INPUT, - MUX_IN_FEC_FEC_RX_DV_SELECT_INPUT, - MUX_IN_FEC_FEC_RX_ER_SELECT_INPUT, - MUX_IN_FEC_FEC_TX_CLK_SELECT_INPUT, - MUX_IN_GPIO3_IPP_IND_G_IN_1_SELECT_INPUT, - MUX_IN_GPIO3_IPP_IND_G_IN_2_SELECT_INPUT, - MUX_IN_GPIO3_IPP_IND_G_IN_3_SELECT_INPUT, - MUX_IN_GPIO3_IPP_IND_G_IN_4_SELECT_INPUT, - MUX_IN_GPIO3_IPP_IND_G_IN_5_SELECT_INPUT, - MUX_IN_GPIO3_IPP_IND_G_IN_6_SELECT_INPUT, - MUX_IN_GPIO3_IPP_IND_G_IN_7_SELECT_INPUT, - MUX_IN_GPIO3_IPP_IND_G_IN_8_SELECT_INPUT, - /* TO2 */ - MUX_IN_GPIO3_IPP_IND_G_IN_12_SELECT_INPUT, - MUX_IN_HSC_MIPI_MIX_IPP_IND_SENS1_DATA_EN_SELECT_INPUT, - MUX_IN_HSC_MIPI_MIX_IPP_IND_SENS2_DATA_EN_SELECT_INPUT, - /* TO2 */ - MUX_IN_HSC_MIPI_MIX_PAR_VSYNC_SELECT_INPUT, - /* TO2 */ - MUX_IN_HSC_MIPI_MIX_PAR_DI_WAIT_SELECT_INPUT, - MUX_IN_HSC_MIPI_MIX_PAR_SISG_TRIG_SELECT_INPUT, - MUX_IN_I2C1_IPP_SCL_IN_SELECT_INPUT, - MUX_IN_I2C1_IPP_SDA_IN_SELECT_INPUT, - MUX_IN_I2C2_IPP_SCL_IN_SELECT_INPUT, - MUX_IN_I2C2_IPP_SDA_IN_SELECT_INPUT, - - MUX_IN_IPU_IPP_DI_0_IND_DISPB_SD_D_SELECT_INPUT, - - MUX_IN_IPU_IPP_DI_1_IND_DISPB_SD_D_SELECT_INPUT, - - MUX_IN_KPP_IPP_IND_COL_6_SELECT_INPUT, - MUX_IN_KPP_IPP_IND_COL_7_SELECT_INPUT, - MUX_IN_KPP_IPP_IND_ROW_4_SELECT_INPUT, - MUX_IN_KPP_IPP_IND_ROW_5_SELECT_INPUT, - MUX_IN_KPP_IPP_IND_ROW_6_SELECT_INPUT, - MUX_IN_KPP_IPP_IND_ROW_7_SELECT_INPUT, - MUX_IN_UART1_IPP_UART_RTS_B_SELECT_INPUT, - MUX_IN_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, - MUX_IN_UART2_IPP_UART_RTS_B_SELECT_INPUT, - MUX_IN_UART2_IPP_UART_RXD_MUX_SELECT_INPUT, - MUX_IN_UART3_IPP_UART_RTS_B_SELECT_INPUT, - MUX_IN_UART3_IPP_UART_RXD_MUX_SELECT_INPUT, - MUX_IN_USBOH3_IPP_IND_UH3_CLK_SELECT_INPUT, - MUX_IN_USBOH3_IPP_IND_UH3_DATA_0_SELECT_INPUT, - MUX_IN_USBOH3_IPP_IND_UH3_DATA_1_SELECT_INPUT, - MUX_IN_USBOH3_IPP_IND_UH3_DATA_2_SELECT_INPUT, - MUX_IN_USBOH3_IPP_IND_UH3_DATA_3_SELECT_INPUT, - MUX_IN_USBOH3_IPP_IND_UH3_DATA_4_SELECT_INPUT, - MUX_IN_USBOH3_IPP_IND_UH3_DATA_5_SELECT_INPUT, - MUX_IN_USBOH3_IPP_IND_UH3_DATA_6_SELECT_INPUT, - MUX_IN_USBOH3_IPP_IND_UH3_DATA_7_SELECT_INPUT, - MUX_IN_USBOH3_IPP_IND_UH3_DIR_SELECT_INPUT, - MUX_IN_USBOH3_IPP_IND_UH3_NXT_SELECT_INPUT, - MUX_IN_USBOH3_IPP_IND_UH3_STP_SELECT_INPUT, - MUX_INPUT_NUM_MUX, -} iomux_input_select_t; - -/*! * various IOMUX input functions */ typedef enum iomux_input_config { @@ -243,4 +199,4 @@ unsigned int mxc_iomux_get_pad(iomux_pin_name_t pin); */ void mxc_iomux_set_input(iomux_input_select_t input, u32 config); -#endif /* __MACH_MX51_IOMUX_H__ */ +#endif /* __MACH_MX5_IOMUX_H__ */ diff --git a/arch/arm/mach-mx5/mm.c b/arch/arm/mach-mx5/mm.c index 39222b8d1c55..810cb1bf1ca8 100644 --- a/arch/arm/mach-mx5/mm.c +++ b/arch/arm/mach-mx5/mm.c @@ -28,7 +28,7 @@ /*! * This structure defines the MX51 memory map. */ -static struct map_desc mx51_io_desc[] __initdata = { +static struct map_desc mx5_io_desc[] __initdata = { { .virtual = AIPS1_BASE_ADDR_VIRT, .pfn = __phys_to_pfn(AIPS1_BASE_ADDR), @@ -44,11 +44,6 @@ static struct map_desc mx51_io_desc[] __initdata = { .pfn = __phys_to_pfn(AIPS2_BASE_ADDR), .length = AIPS2_SIZE, .type = MT_DEVICE}, - { - .virtual = NFC_BASE_ADDR_AXI_VIRT, - .pfn = __phys_to_pfn(NFC_BASE_ADDR_AXI), - .length = NFC_AXI_SIZE, - .type = MT_DEVICE}, }; /*! @@ -56,7 +51,15 @@ static struct map_desc mx51_io_desc[] __initdata = { * system startup to create static physical to virtual memory map for * the IO modules. */ -void __init mx51_map_io(void) +void __init mx5_map_io(void) { - iotable_init(mx51_io_desc, ARRAY_SIZE(mx51_io_desc)); + int i; + + /* Fixup the mappings for MX53 */ + if (cpu_is_mx53()) { + for (i = 0; i < ARRAY_SIZE(mx5_io_desc); i++) + mx5_io_desc[i].pfn -= __phys_to_pfn(0x20000000); + } + + iotable_init(mx5_io_desc, ARRAY_SIZE(mx5_io_desc)); } diff --git a/arch/arm/mach-mx5/mx51_3stack.c b/arch/arm/mach-mx5/mx51_3stack.c index 995cd36b220a..7e992c50cb59 100644 --- a/arch/arm/mach-mx5/mx51_3stack.c +++ b/arch/arm/mach-mx5/mx51_3stack.c @@ -49,6 +49,7 @@ #include "devices.h" #include "board-mx51_3stack.h" #include "iomux.h" +#include "mx51_pins.h" #include "crm_regs.h" #include "usb.h" @@ -836,7 +837,7 @@ EXPORT_SYMBOL(get_unifi_plat_data); static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags, char **cmdline, struct meminfo *mi) { - mxc_cpu_init(); + mxc_set_cpu_type(MXC_CPU_MX51); get_cpu_wp = mx51_3stack_get_cpu_wp; set_num_cpu_wp = mx51_3stack_set_num_cpu_wp; @@ -991,10 +992,9 @@ MACHINE_START(MX51_3DS, "Freescale MX51 3-Stack Board") /* Maintainer: Freescale Semiconductor, Inc. */ .phys_io = AIPS1_BASE_ADDR, .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, - .boot_params = PHYS_OFFSET + 0x100, .fixup = fixup_mxc_board, - .map_io = mx51_map_io, - .init_irq = mx51_init_irq, + .map_io = mx5_map_io, + .init_irq = mx5_init_irq, .init_machine = mxc_board_init, .timer = &mxc_timer, MACHINE_END diff --git a/arch/arm/mach-mx5/mx51_3stack_gpio.c b/arch/arm/mach-mx5/mx51_3stack_gpio.c index dd08add0fa5b..b0fca773eaaa 100644 --- a/arch/arm/mach-mx5/mx51_3stack_gpio.c +++ b/arch/arm/mach-mx5/mx51_3stack_gpio.c @@ -1,5 +1,5 @@ /* - * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. */ /* @@ -21,9 +21,10 @@ #include <mach/gpio.h> #include "iomux.h" +#include "mx51_pins.h" /*! - * @file mach-mx51/mx51_3stack_gpio.c + * @file mach-mx5/mx51_3stack_gpio.c * * @brief This file contains all the GPIO setup functions for the board. * diff --git a/arch/arm/mach-mx5/mx51_3stack_pmic_mc13892.c b/arch/arm/mach-mx5/mx51_3stack_pmic_mc13892.c index 7b4cd31ae4f0..6206b62587b0 100644 --- a/arch/arm/mach-mx5/mx51_3stack_pmic_mc13892.c +++ b/arch/arm/mach-mx5/mx51_3stack_pmic_mc13892.c @@ -24,6 +24,7 @@ #include <linux/mfd/mc13892/core.h> #include <mach/irqs.h> #include "iomux.h" +#include "mx51_pins.h" /* * Convenience conversion. diff --git a/arch/arm/mach-mx5/mx51_babbage.c b/arch/arm/mach-mx5/mx51_babbage.c index ab7dd288365f..e346c2e2b347 100644 --- a/arch/arm/mach-mx5/mx51_babbage.c +++ b/arch/arm/mach-mx5/mx51_babbage.c @@ -47,6 +47,7 @@ #include "devices.h" #include "board-mx51_babbage.h" #include "iomux.h" +#include "mx51_pins.h" #include "crm_regs.h" #include "usb.h" @@ -798,7 +799,7 @@ static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags, int size = SZ_512M - SZ_32M; struct tag *t; - mxc_cpu_init(); + mxc_set_cpu_type(MXC_CPU_MX51); get_cpu_wp = mx51_babbage_get_cpu_wp; set_num_cpu_wp = mx51_babbage_set_num_cpu_wp; @@ -984,10 +985,9 @@ static struct sys_timer mxc_timer = { /* *INDENT-OFF* */ MACHINE_START(MX51_BABBAGE, "Freescale MX51 Babbage Board") /* Maintainer: Freescale Semiconductor, Inc. */ - .boot_params = PHYS_OFFSET + 0x100, .fixup = fixup_mxc_board, - .map_io = mx51_map_io, - .init_irq = mx51_init_irq, + .map_io = mx5_map_io, + .init_irq = mx5_init_irq, .init_machine = mxc_board_init, .timer = &mxc_timer, MACHINE_END diff --git a/arch/arm/mach-mx5/mx51_babbage_gpio.c b/arch/arm/mach-mx5/mx51_babbage_gpio.c index 58324efb6a75..4b3e2ee73faf 100644 --- a/arch/arm/mach-mx5/mx51_babbage_gpio.c +++ b/arch/arm/mach-mx5/mx51_babbage_gpio.c @@ -1,5 +1,5 @@ /* - * Copyright 2007-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2007-2010 Freescale Semiconductor, Inc. All Rights Reserved. */ /* @@ -19,9 +19,9 @@ #include <mach/gpio.h> #include "iomux.h" - +#include "mx51_pins.h" /*! - * @file mach-mx51/mx51_babbage_gpio.c + * @file mach-mx5/mx51_babbage_gpio.c * * @brief This file contains all the GPIO setup functions for the board. * diff --git a/arch/arm/mach-mx5/mx51_babbage_pmic_mc13892.c b/arch/arm/mach-mx5/mx51_babbage_pmic_mc13892.c index 5f703fbff140..cb442e4aa2fd 100644 --- a/arch/arm/mach-mx5/mx51_babbage_pmic_mc13892.c +++ b/arch/arm/mach-mx5/mx51_babbage_pmic_mc13892.c @@ -24,6 +24,7 @@ #include <linux/mfd/mc13892/core.h> #include <mach/irqs.h> #include "iomux.h" +#include "mx51_pins.h" /* * Convenience conversion. diff --git a/arch/arm/mach-mx5/mx51_pins.h b/arch/arm/mach-mx5/mx51_pins.h index c0905a025556..351cdb29a32a 100644 --- a/arch/arm/mach-mx5/mx51_pins.h +++ b/arch/arm/mach-mx5/mx51_pins.h @@ -1,5 +1,5 @@ /* - * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. */ /* @@ -12,6 +12,7 @@ */ #ifndef __ASM_ARCH_MXC_MX51_PINS_H__ #define __ASM_ARCH_MXC_MX51_PINS_H__ +#include "iomux.h" /*! * @file arch-mxc/mx51_pins.h @@ -23,338 +24,385 @@ #ifndef __ASSEMBLY__ -/*! - * @name IOMUX/PAD Bit field definitions - */ - -/*! @{ */ - -/*! - * In order to identify pins more effectively, each mux-controlled pin's - * enumerated value is constructed in the following way: - * - * ------------------------------------------------------------------- - * 31-29 | 28 - 24 | 23 - 21 | 20 - 10| 9 - 0 - * ------------------------------------------------------------------- - * IO_P | IO_I | GPIO_I | PAD_I | MUX_I - * ------------------------------------------------------------------- - * - * Bit 0 to 9 contains MUX_I used to identify the register - * offset (0-based. base is IOMUX_module_base) defined in the Section - * "sw_pad_ctl & sw_mux_ctl details" of the IC Spec. The - * similar field definitions are used for the pad control register. - * For example, the MX51_PIN_ETM_D0 is defined in the enumeration: - * ( (0x28 - MUX_I_START) << MUX_I)|( (0x250 - PAD_I_START) << PAD_I) - * It means the mux control register is at register offset 0x28. The pad control - * register offset is: 0x250 and also occupy the least significant bits - * within the register. - */ - -/*! - * Starting bit position within each entry of \b iomux_pins to represent the - * MUX control register offset - */ -#define MUX_I 0 -/*! - * Starting bit position within each entry of \b iomux_pins to represent the - * PAD control register offset - */ -#define PAD_I 10 -/*! - * Starting bit position within each entry of \b iomux_pins to represent which - * mux mode is for GPIO (0-based) - */ -#define GPIO_I 21 +#define PAD_I_START_MX51 0x3F0 +#define INPUT_CTL_START_MX51 0x8C4 +#define INPUT_CTL_START_MX51_TO1 0x928 -#define NON_GPIO_PORT 0x7 -#define PIN_TO_MUX_MASK ((1 << (PAD_I - MUX_I)) - 1) -#define PIN_TO_PAD_MASK ((1 << (GPIO_I - PAD_I)) - 1) -#define PIN_TO_ALT_GPIO_MASK ((1 << (MUX_IO_I - GPIO_I)) - 1) +#define MUX_I_END_MX51 (PAD_I_START_MX51 - 4) -#define NON_MUX_I PIN_TO_MUX_MASK -#define MUX_I_START 0x001C -#define PAD_I_START 0x3F0 -#define INPUT_CTL_START 0x8C4 -#define INPUT_CTL_START_TO1 0x928 -#define MUX_I_END (PAD_I_START - 4) - -#define _MXC_BUILD_PIN(gp, gi, ga, mi, pi) \ +#define _MXC_BUILD_PIN_MX51(gp, gi, ga, mi, pi) \ (((gp) << MUX_IO_P) | ((gi) << MUX_IO_I) | \ ((mi) << MUX_I) | \ - ((pi - PAD_I_START) << PAD_I) | \ + ((pi - PAD_I_START_MX51) << PAD_I) | \ ((ga) << GPIO_I)) -#define _MXC_BUILD_GPIO_PIN(gp, gi, ga, mi, pi) \ - _MXC_BUILD_PIN(gp, gi, ga, mi, pi) - -#define _MXC_BUILD_NON_GPIO_PIN(mi, pi) \ - _MXC_BUILD_PIN(NON_GPIO_PORT, 0, 0, mi, pi) - -#define PIN_TO_IOMUX_MUX(pin) ((pin >> MUX_I) & PIN_TO_MUX_MASK) -#define PIN_TO_IOMUX_PAD(pin) ((pin >> PAD_I) & PIN_TO_PAD_MASK) -#define PIN_TO_ALT_GPIO(pin) ((pin >> GPIO_I) & PIN_TO_ALT_GPIO_MASK) -#define PIN_TO_IOMUX_INDEX(pin) (PIN_TO_IOMUX_MUX(pin) >> 2) - -/*! @} End IOMUX/PAD Bit field definitions */ +#define _MXC_BUILD_GPIO_PIN_MX51(gp, gi, ga, mi, pi) \ + _MXC_BUILD_PIN_MX51(gp, gi, ga, mi, pi) +#define _MXC_BUILD_NON_GPIO_PIN_MX51(mi, pi) \ + _MXC_BUILD_PIN_MX51(NON_GPIO_PORT, 0, 0, mi, pi) /*! * This enumeration is constructed based on the Section * "sw_pad_ctl & sw_mux_ctl details" of the MX51 IC Spec. Each enumerated * value is constructed based on the rules described above. */ -enum iomux_pins { - MX51_PIN_EIM_DA0 = _MXC_BUILD_NON_GPIO_PIN(0x1C, 0x7A8), - MX51_PIN_EIM_DA1 = _MXC_BUILD_NON_GPIO_PIN(0x20, 0x7A8), - MX51_PIN_EIM_DA2 = _MXC_BUILD_NON_GPIO_PIN(0x24, 0x7A8), - MX51_PIN_EIM_DA3 = _MXC_BUILD_NON_GPIO_PIN(0x28, 0x7A8), - MX51_PIN_EIM_DA4 = _MXC_BUILD_NON_GPIO_PIN(0x2C, 0x7AC), - MX51_PIN_EIM_DA5 = _MXC_BUILD_NON_GPIO_PIN(0x30, 0x7AC), - MX51_PIN_EIM_DA6 = _MXC_BUILD_NON_GPIO_PIN(0x34, 0x7AC), - MX51_PIN_EIM_DA7 = _MXC_BUILD_NON_GPIO_PIN(0x38, 0x7AC), - MX51_PIN_EIM_DA8 = _MXC_BUILD_NON_GPIO_PIN(0x3C, 0x7B0), - MX51_PIN_EIM_DA9 = _MXC_BUILD_NON_GPIO_PIN(0x40, 0x7B0), - MX51_PIN_EIM_DA10 = _MXC_BUILD_NON_GPIO_PIN(0x44, 0x7B0), - MX51_PIN_EIM_DA11 = _MXC_BUILD_NON_GPIO_PIN(0x48, 0x7B0), - MX51_PIN_EIM_DA12 = _MXC_BUILD_NON_GPIO_PIN(0x4C, 0x7BC), - MX51_PIN_EIM_DA13 = _MXC_BUILD_NON_GPIO_PIN(0x50, 0x7BC), - MX51_PIN_EIM_DA14 = _MXC_BUILD_NON_GPIO_PIN(0x54, 0x7BC), - MX51_PIN_EIM_DA15 = _MXC_BUILD_NON_GPIO_PIN(0x58, 0x7BC), - MX51_PIN_EIM_D16 = _MXC_BUILD_GPIO_PIN(1, 0, 1, 0x5C, 0x3F0), - MX51_PIN_EIM_D17 = _MXC_BUILD_GPIO_PIN(1, 1, 1, 0x60, 0x3F4), - MX51_PIN_EIM_D18 = _MXC_BUILD_GPIO_PIN(1, 2, 1, 0x64, 0x3F8), - MX51_PIN_EIM_D19 = _MXC_BUILD_GPIO_PIN(1, 3, 1, 0x68, 0x3FC), - MX51_PIN_EIM_D20 = _MXC_BUILD_GPIO_PIN(1, 4, 1, 0x6C, 0x400), - MX51_PIN_EIM_D21 = _MXC_BUILD_GPIO_PIN(1, 5, 1, 0x70, 0x404), - MX51_PIN_EIM_D22 = _MXC_BUILD_GPIO_PIN(1, 6, 1, 0x74, 0x408), - MX51_PIN_EIM_D23 = _MXC_BUILD_GPIO_PIN(1, 7, 1, 0x78, 0x40C), - MX51_PIN_EIM_D24 = _MXC_BUILD_GPIO_PIN(1, 8, 1, 0x7C, 0x410), - MX51_PIN_EIM_D25 = _MXC_BUILD_NON_GPIO_PIN(0x80, 0x414), - MX51_PIN_EIM_D26 = _MXC_BUILD_NON_GPIO_PIN(0x84, 0x418), - MX51_PIN_EIM_D27 = _MXC_BUILD_GPIO_PIN(1, 9, 1, 0x88, 0x41C), - MX51_PIN_EIM_D28 = _MXC_BUILD_NON_GPIO_PIN(0x8C, 0x420), - MX51_PIN_EIM_D29 = _MXC_BUILD_NON_GPIO_PIN(0x90, 0x424), - MX51_PIN_EIM_D30 = _MXC_BUILD_NON_GPIO_PIN(0x94, 0x428), - MX51_PIN_EIM_D31 = _MXC_BUILD_NON_GPIO_PIN(0x98, 0x42C), - MX51_PIN_EIM_A16 = _MXC_BUILD_GPIO_PIN(1, 10, 1, 0x9C, 0x430), - MX51_PIN_EIM_A17 = _MXC_BUILD_GPIO_PIN(1, 11, 1, 0xA0, 0x434), - MX51_PIN_EIM_A18 = _MXC_BUILD_GPIO_PIN(1, 12, 1, 0xA4, 0x438), - MX51_PIN_EIM_A19 = _MXC_BUILD_GPIO_PIN(1, 13, 1, 0xA8, 0x43C), - MX51_PIN_EIM_A20 = _MXC_BUILD_GPIO_PIN(1, 14, 1, 0xAC, 0x440), - MX51_PIN_EIM_A21 = _MXC_BUILD_GPIO_PIN(1, 15, 1, 0xB0, 0x444), - MX51_PIN_EIM_A22 = _MXC_BUILD_GPIO_PIN(1, 16, 1, 0xB4, 0x448), - MX51_PIN_EIM_A23 = _MXC_BUILD_GPIO_PIN(1, 17, 1, 0xB8, 0x44C), - MX51_PIN_EIM_A24 = _MXC_BUILD_GPIO_PIN(1, 18, 1, 0xBC, 0x450), - MX51_PIN_EIM_A25 = _MXC_BUILD_GPIO_PIN(1, 19, 1, 0xC0, 0x454), - MX51_PIN_EIM_A26 = _MXC_BUILD_GPIO_PIN(1, 20, 1, 0xC4, 0x458), - MX51_PIN_EIM_A27 = _MXC_BUILD_GPIO_PIN(1, 21, 1, 0xC8, 0x45C), - MX51_PIN_EIM_EB0 = _MXC_BUILD_NON_GPIO_PIN(0xCC, 0x460), - MX51_PIN_EIM_EB1 = _MXC_BUILD_NON_GPIO_PIN(0xD0, 0x464), - MX51_PIN_EIM_EB2 = _MXC_BUILD_GPIO_PIN(1, 22, 1, 0xD4, 0x468), - MX51_PIN_EIM_EB3 = _MXC_BUILD_GPIO_PIN(1, 23, 1, 0xD8, 0x46C), - MX51_PIN_EIM_OE = _MXC_BUILD_GPIO_PIN(1, 24, 1, 0xDC, 0x470), - MX51_PIN_EIM_CS0 = _MXC_BUILD_GPIO_PIN(1, 25, 1, 0xE0, 0x474), - MX51_PIN_EIM_CS1 = _MXC_BUILD_GPIO_PIN(1, 26, 1, 0xE4, 0x478), - MX51_PIN_EIM_CS2 = _MXC_BUILD_GPIO_PIN(1, 27, 1, 0xE8, 0x47C), - MX51_PIN_EIM_CS3 = _MXC_BUILD_GPIO_PIN(1, 28, 1, 0xEC, 0x480), - MX51_PIN_EIM_CS4 = _MXC_BUILD_GPIO_PIN(1, 29, 1, 0xF0, 0x484), - MX51_PIN_EIM_CS5 = _MXC_BUILD_GPIO_PIN(1, 30, 1, 0xF4, 0x488), - MX51_PIN_EIM_DTACK = _MXC_BUILD_GPIO_PIN(1, 31, 1, 0xF8, 0x48C), - MX51_PIN_EIM_LBA = _MXC_BUILD_GPIO_PIN(2, 1, 1, 0xFC, 0x494), - MX51_PIN_EIM_CRE = _MXC_BUILD_GPIO_PIN(2, 2, 1, 0x100, 0x4A0), - MX51_PIN_DRAM_CS1 = _MXC_BUILD_NON_GPIO_PIN(0x104, 0x4D0), - MX51_PIN_NANDF_WE_B = _MXC_BUILD_GPIO_PIN(2, 3, 3, 0x108, 0x4E4), - MX51_PIN_NANDF_RE_B = _MXC_BUILD_GPIO_PIN(2, 4, 3, 0x10C, 0x4E8), - MX51_PIN_NANDF_ALE = _MXC_BUILD_GPIO_PIN(2, 5, 3, 0x110, 0x4EC), - MX51_PIN_NANDF_CLE = _MXC_BUILD_GPIO_PIN(2, 6, 3, 0x114, 0x4F0), - MX51_PIN_NANDF_WP_B = _MXC_BUILD_GPIO_PIN(2, 7, 3, 0x118, 0x4F4), - MX51_PIN_NANDF_RB0 = _MXC_BUILD_GPIO_PIN(2, 8, 3, 0x11C, 0x4F8), - MX51_PIN_NANDF_RB1 = _MXC_BUILD_GPIO_PIN(2, 9, 3, 0x120, 0x4FC), - MX51_PIN_NANDF_RB2 = _MXC_BUILD_GPIO_PIN(2, 10, 3, 0x124, 0x500), - MX51_PIN_NANDF_RB3 = _MXC_BUILD_GPIO_PIN(2, 11, 3, 0x128, 0x504), - MX51_PIN_GPIO_NAND = _MXC_BUILD_GPIO_PIN(2, 12, 3, 0x12C, 0x514), +enum iomux_pins_mx51 { + MX51_PIN_EIM_DA0 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x1C, 0x7A8), + MX51_PIN_EIM_DA1 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x20, 0x7A8), + MX51_PIN_EIM_DA2 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x24, 0x7A8), + MX51_PIN_EIM_DA3 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x28, 0x7A8), + MX51_PIN_EIM_DA4 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x2C, 0x7AC), + MX51_PIN_EIM_DA5 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x30, 0x7AC), + MX51_PIN_EIM_DA6 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x34, 0x7AC), + MX51_PIN_EIM_DA7 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x38, 0x7AC), + MX51_PIN_EIM_DA8 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x3C, 0x7B0), + MX51_PIN_EIM_DA9 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x40, 0x7B0), + MX51_PIN_EIM_DA10 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x44, 0x7B0), + MX51_PIN_EIM_DA11 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x48, 0x7B0), + MX51_PIN_EIM_DA12 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x4C, 0x7BC), + MX51_PIN_EIM_DA13 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x50, 0x7BC), + MX51_PIN_EIM_DA14 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x54, 0x7BC), + MX51_PIN_EIM_DA15 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x58, 0x7BC), + MX51_PIN_EIM_D16 = _MXC_BUILD_GPIO_PIN_MX51(1, 0, 1, 0x5C, 0x3F0), + MX51_PIN_EIM_D17 = _MXC_BUILD_GPIO_PIN_MX51(1, 1, 1, 0x60, 0x3F4), + MX51_PIN_EIM_D18 = _MXC_BUILD_GPIO_PIN_MX51(1, 2, 1, 0x64, 0x3F8), + MX51_PIN_EIM_D19 = _MXC_BUILD_GPIO_PIN_MX51(1, 3, 1, 0x68, 0x3FC), + MX51_PIN_EIM_D20 = _MXC_BUILD_GPIO_PIN_MX51(1, 4, 1, 0x6C, 0x400), + MX51_PIN_EIM_D21 = _MXC_BUILD_GPIO_PIN_MX51(1, 5, 1, 0x70, 0x404), + MX51_PIN_EIM_D22 = _MXC_BUILD_GPIO_PIN_MX51(1, 6, 1, 0x74, 0x408), + MX51_PIN_EIM_D23 = _MXC_BUILD_GPIO_PIN_MX51(1, 7, 1, 0x78, 0x40C), + MX51_PIN_EIM_D24 = _MXC_BUILD_GPIO_PIN_MX51(1, 8, 1, 0x7C, 0x410), + MX51_PIN_EIM_D25 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x80, 0x414), + MX51_PIN_EIM_D26 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x84, 0x418), + MX51_PIN_EIM_D27 = _MXC_BUILD_GPIO_PIN_MX51(1, 9, 1, 0x88, 0x41C), + MX51_PIN_EIM_D28 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x8C, 0x420), + MX51_PIN_EIM_D29 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x90, 0x424), + MX51_PIN_EIM_D30 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x94, 0x428), + MX51_PIN_EIM_D31 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x98, 0x42C), + MX51_PIN_EIM_A16 = _MXC_BUILD_GPIO_PIN_MX51(1, 10, 1, 0x9C, 0x430), + MX51_PIN_EIM_A17 = _MXC_BUILD_GPIO_PIN_MX51(1, 11, 1, 0xA0, 0x434), + MX51_PIN_EIM_A18 = _MXC_BUILD_GPIO_PIN_MX51(1, 12, 1, 0xA4, 0x438), + MX51_PIN_EIM_A19 = _MXC_BUILD_GPIO_PIN_MX51(1, 13, 1, 0xA8, 0x43C), + MX51_PIN_EIM_A20 = _MXC_BUILD_GPIO_PIN_MX51(1, 14, 1, 0xAC, 0x440), + MX51_PIN_EIM_A21 = _MXC_BUILD_GPIO_PIN_MX51(1, 15, 1, 0xB0, 0x444), + MX51_PIN_EIM_A22 = _MXC_BUILD_GPIO_PIN_MX51(1, 16, 1, 0xB4, 0x448), + MX51_PIN_EIM_A23 = _MXC_BUILD_GPIO_PIN_MX51(1, 17, 1, 0xB8, 0x44C), + MX51_PIN_EIM_A24 = _MXC_BUILD_GPIO_PIN_MX51(1, 18, 1, 0xBC, 0x450), + MX51_PIN_EIM_A25 = _MXC_BUILD_GPIO_PIN_MX51(1, 19, 1, 0xC0, 0x454), + MX51_PIN_EIM_A26 = _MXC_BUILD_GPIO_PIN_MX51(1, 20, 1, 0xC4, 0x458), + MX51_PIN_EIM_A27 = _MXC_BUILD_GPIO_PIN_MX51(1, 21, 1, 0xC8, 0x45C), + MX51_PIN_EIM_EB0 = _MXC_BUILD_NON_GPIO_PIN_MX51(0xCC, 0x460), + MX51_PIN_EIM_EB1 = _MXC_BUILD_NON_GPIO_PIN_MX51(0xD0, 0x464), + MX51_PIN_EIM_EB2 = _MXC_BUILD_GPIO_PIN_MX51(1, 22, 1, 0xD4, 0x468), + MX51_PIN_EIM_EB3 = _MXC_BUILD_GPIO_PIN_MX51(1, 23, 1, 0xD8, 0x46C), + MX51_PIN_EIM_OE = _MXC_BUILD_GPIO_PIN_MX51(1, 24, 1, 0xDC, 0x470), + MX51_PIN_EIM_CS0 = _MXC_BUILD_GPIO_PIN_MX51(1, 25, 1, 0xE0, 0x474), + MX51_PIN_EIM_CS1 = _MXC_BUILD_GPIO_PIN_MX51(1, 26, 1, 0xE4, 0x478), + MX51_PIN_EIM_CS2 = _MXC_BUILD_GPIO_PIN_MX51(1, 27, 1, 0xE8, 0x47C), + MX51_PIN_EIM_CS3 = _MXC_BUILD_GPIO_PIN_MX51(1, 28, 1, 0xEC, 0x480), + MX51_PIN_EIM_CS4 = _MXC_BUILD_GPIO_PIN_MX51(1, 29, 1, 0xF0, 0x484), + MX51_PIN_EIM_CS5 = _MXC_BUILD_GPIO_PIN_MX51(1, 30, 1, 0xF4, 0x488), + MX51_PIN_EIM_DTACK = _MXC_BUILD_GPIO_PIN_MX51(1, 31, 1, 0xF8, 0x48C), + MX51_PIN_EIM_LBA = _MXC_BUILD_GPIO_PIN_MX51(2, 1, 1, 0xFC, 0x494), + MX51_PIN_EIM_CRE = _MXC_BUILD_GPIO_PIN_MX51(2, 2, 1, 0x100, 0x4A0), + MX51_PIN_DRAM_CS1 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x104, 0x4D0), + MX51_PIN_NANDF_WE_B = _MXC_BUILD_GPIO_PIN_MX51(2, 3, 3, 0x108, 0x4E4), + MX51_PIN_NANDF_RE_B = _MXC_BUILD_GPIO_PIN_MX51(2, 4, 3, 0x10C, 0x4E8), + MX51_PIN_NANDF_ALE = _MXC_BUILD_GPIO_PIN_MX51(2, 5, 3, 0x110, 0x4EC), + MX51_PIN_NANDF_CLE = _MXC_BUILD_GPIO_PIN_MX51(2, 6, 3, 0x114, 0x4F0), + MX51_PIN_NANDF_WP_B = _MXC_BUILD_GPIO_PIN_MX51(2, 7, 3, 0x118, 0x4F4), + MX51_PIN_NANDF_RB0 = _MXC_BUILD_GPIO_PIN_MX51(2, 8, 3, 0x11C, 0x4F8), + MX51_PIN_NANDF_RB1 = _MXC_BUILD_GPIO_PIN_MX51(2, 9, 3, 0x120, 0x4FC), + MX51_PIN_NANDF_RB2 = _MXC_BUILD_GPIO_PIN_MX51(2, 10, 3, 0x124, 0x500), + MX51_PIN_NANDF_RB3 = _MXC_BUILD_GPIO_PIN_MX51(2, 11, 3, 0x128, 0x504), + MX51_PIN_GPIO_NAND = _MXC_BUILD_GPIO_PIN_MX51(2, 12, 3, 0x12C, 0x514), MX51_PIN_NANDF_RB4 = MX51_PIN_GPIO_NAND, - MX51_PIN_NANDF_RB5 = _MXC_BUILD_GPIO_PIN(2, 13, 3, 0x130, 0x5D8), - MX51_PIN_NANDF_RB6 = _MXC_BUILD_GPIO_PIN(2, 14, 3, 0x134, 0x5DC), - MX51_PIN_NANDF_RB7 = _MXC_BUILD_GPIO_PIN(2, 15, 3, 0x138, 0x5E0), - MX51_PIN_NANDF_CS0 = _MXC_BUILD_GPIO_PIN(2, 16, 3, 0x130, 0x518), - MX51_PIN_NANDF_CS1 = _MXC_BUILD_GPIO_PIN(2, 17, 3, 0x134, 0x51C), - MX51_PIN_NANDF_CS2 = _MXC_BUILD_GPIO_PIN(2, 18, 3, 0x138, 0x520), - MX51_PIN_NANDF_CS3 = _MXC_BUILD_GPIO_PIN(2, 19, 3, 0x13C, 0x524), - MX51_PIN_NANDF_CS4 = _MXC_BUILD_GPIO_PIN(2, 20, 3, 0x140, 0x528), - MX51_PIN_NANDF_CS5 = _MXC_BUILD_GPIO_PIN(2, 21, 3, 0x144, 0x52C), - MX51_PIN_NANDF_CS6 = _MXC_BUILD_GPIO_PIN(2, 22, 3, 0x148, 0x530), - MX51_PIN_NANDF_CS7 = _MXC_BUILD_GPIO_PIN(2, 23, 3, 0x14C, 0x534), - MX51_PIN_NANDF_RDY_INT = _MXC_BUILD_GPIO_PIN(2, 24, 3, 0x150, 0x538), - MX51_PIN_NANDF_D15 = _MXC_BUILD_GPIO_PIN(2, 25, 3, 0x154, 0x53C), - MX51_PIN_NANDF_D14 = _MXC_BUILD_GPIO_PIN(2, 26, 3, 0x158, 0x540), - MX51_PIN_NANDF_D13 = _MXC_BUILD_GPIO_PIN(2, 27, 3, 0x15C, 0x544), - MX51_PIN_NANDF_D12 = _MXC_BUILD_GPIO_PIN(2, 28, 3, 0x160, 0x548), - MX51_PIN_NANDF_D11 = _MXC_BUILD_GPIO_PIN(2, 29, 3, 0x164, 0x54C), - MX51_PIN_NANDF_D10 = _MXC_BUILD_GPIO_PIN(2, 30, 3, 0x168, 0x550), - MX51_PIN_NANDF_D9 = _MXC_BUILD_GPIO_PIN(2, 31, 3, 0x16C, 0x554), - MX51_PIN_NANDF_D8 = _MXC_BUILD_GPIO_PIN(3, 0, 3, 0x170, 0x558), - MX51_PIN_NANDF_D7 = _MXC_BUILD_GPIO_PIN(3, 1, 3, 0x174, 0x55C), - MX51_PIN_NANDF_D6 = _MXC_BUILD_GPIO_PIN(3, 2, 3, 0x178, 0x560), - MX51_PIN_NANDF_D5 = _MXC_BUILD_GPIO_PIN(3, 3, 3, 0x17C, 0x564), - MX51_PIN_NANDF_D4 = _MXC_BUILD_GPIO_PIN(3, 4, 3, 0x180, 0x568), - MX51_PIN_NANDF_D3 = _MXC_BUILD_GPIO_PIN(3, 5, 3, 0x184, 0x56C), - MX51_PIN_NANDF_D2 = _MXC_BUILD_GPIO_PIN(3, 6, 3, 0x188, 0x570), - MX51_PIN_NANDF_D1 = _MXC_BUILD_GPIO_PIN(3, 7, 3, 0x18C, 0x574), - MX51_PIN_NANDF_D0 = _MXC_BUILD_GPIO_PIN(3, 8, 3, 0x190, 0x578), - MX51_PIN_CSI1_D8 = _MXC_BUILD_GPIO_PIN(2, 12, 3, 0x194, 0x57C), - MX51_PIN_CSI1_D9 = _MXC_BUILD_GPIO_PIN(2, 13, 3, 0x198, 0x580), - MX51_PIN_CSI1_D10 = _MXC_BUILD_NON_GPIO_PIN(0x19C, 0x584), - MX51_PIN_CSI1_D11 = _MXC_BUILD_NON_GPIO_PIN(0x1A0, 0x588), - MX51_PIN_CSI1_D12 = _MXC_BUILD_NON_GPIO_PIN(0x1A4, 0x58C), - MX51_PIN_CSI1_D13 = _MXC_BUILD_NON_GPIO_PIN(0x1A8, 0x590), - MX51_PIN_CSI1_D14 = _MXC_BUILD_NON_GPIO_PIN(0x1AC, 0x594), - MX51_PIN_CSI1_D15 = _MXC_BUILD_NON_GPIO_PIN(0x1B0, 0x598), - MX51_PIN_CSI1_D16 = _MXC_BUILD_NON_GPIO_PIN(0x1B4, 0x59C), - MX51_PIN_CSI1_D17 = _MXC_BUILD_NON_GPIO_PIN(0x1B8, 0x5A0), - MX51_PIN_CSI1_D18 = _MXC_BUILD_NON_GPIO_PIN(0x1BC, 0x5A4), - MX51_PIN_CSI1_D19 = _MXC_BUILD_NON_GPIO_PIN(0x1C0, 0x5A8), - MX51_PIN_CSI1_VSYNC = _MXC_BUILD_GPIO_PIN(2, 14, 3, 0x1C4, 0x5AC), - MX51_PIN_CSI1_HSYNC = _MXC_BUILD_GPIO_PIN(2, 15, 3, 0x1C8, 0x5B0), - MX51_PIN_CSI1_PIXCLK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x5B4), - MX51_PIN_CSI1_MCLK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x5B8), - MX51_PIN_CSI1_PKE0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x860), - MX51_PIN_CSI2_D12 = _MXC_BUILD_GPIO_PIN(3, 9, 3, 0x1CC, 0x5BC), - MX51_PIN_CSI2_D13 = _MXC_BUILD_GPIO_PIN(3, 10, 3, 0x1D0, 0x5C0), - MX51_PIN_CSI2_D14 = _MXC_BUILD_GPIO_PIN(3, 11, 3, 0x1D4, 0x5C4), - MX51_PIN_CSI2_D15 = _MXC_BUILD_GPIO_PIN(3, 12, 3, 0x1D8, 0x5C8), - MX51_PIN_CSI2_D16 = _MXC_BUILD_GPIO_PIN(3, 11, 3, 0x1DC, 0x5CC), - MX51_PIN_CSI2_D17 = _MXC_BUILD_GPIO_PIN(3, 12, 3, 0x1E0, 0x5D0), - MX51_PIN_CSI2_D18 = _MXC_BUILD_GPIO_PIN(3, 11, 3, 0x1E4, 0x5D4), - MX51_PIN_CSI2_D19 = _MXC_BUILD_GPIO_PIN(3, 12, 3, 0x1E8, 0x5D8), - MX51_PIN_CSI2_VSYNC = _MXC_BUILD_GPIO_PIN(3, 13, 3, 0x1EC, 0x5DC), - MX51_PIN_CSI2_HSYNC = _MXC_BUILD_GPIO_PIN(3, 14, 3, 0x1F0, 0x5E0), - MX51_PIN_CSI2_PIXCLK = _MXC_BUILD_GPIO_PIN(3, 15, 3, 0x1F4, 0x5E4), - MX51_PIN_CSI2_PKE0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x81C), - MX51_PIN_I2C1_CLK = _MXC_BUILD_GPIO_PIN(3, 16, 3, 0x1F8, 0x5E8), - MX51_PIN_I2C1_DAT = _MXC_BUILD_GPIO_PIN(3, 17, 3, 0x1FC, 0x5EC), - MX51_PIN_AUD3_BB_TXD = _MXC_BUILD_GPIO_PIN(3, 18, 3, 0x200, 0x5F0), - MX51_PIN_AUD3_BB_RXD = _MXC_BUILD_GPIO_PIN(3, 19, 3, 0x204, 0x5F4), - MX51_PIN_AUD3_BB_CK = _MXC_BUILD_GPIO_PIN(3, 20, 3, 0x208, 0x5F8), - MX51_PIN_AUD3_BB_FS = _MXC_BUILD_GPIO_PIN(3, 21, 3, 0x20C, 0x5FC), - MX51_PIN_CSPI1_MOSI = _MXC_BUILD_GPIO_PIN(3, 22, 3, 0x210, 0x600), - MX51_PIN_CSPI1_MISO = _MXC_BUILD_GPIO_PIN(3, 23, 3, 0x214, 0x604), - MX51_PIN_CSPI1_SS0 = _MXC_BUILD_GPIO_PIN(3, 24, 3, 0x218, 0x608), - MX51_PIN_CSPI1_SS1 = _MXC_BUILD_GPIO_PIN(3, 25, 3, 0x21C, 0x60C), - MX51_PIN_CSPI1_RDY = _MXC_BUILD_GPIO_PIN(3, 26, 3, 0x220, 0x610), - MX51_PIN_CSPI1_SCLK = _MXC_BUILD_GPIO_PIN(3, 27, 3, 0x224, 0x614), - MX51_PIN_UART1_RXD = _MXC_BUILD_GPIO_PIN(3, 28, 3, 0x228, 0x618), - MX51_PIN_UART1_TXD = _MXC_BUILD_GPIO_PIN(3, 29, 3, 0x22C, 0x61C), - MX51_PIN_UART1_RTS = _MXC_BUILD_GPIO_PIN(3, 30, 3, 0x230, 0x620), - MX51_PIN_UART1_CTS = _MXC_BUILD_GPIO_PIN(3, 31, 3, 0x234, 0x624), - MX51_PIN_UART2_RXD = _MXC_BUILD_GPIO_PIN(0, 20, 3, 0x238, 0x628), - MX51_PIN_UART2_TXD = _MXC_BUILD_GPIO_PIN(0, 21, 3, 0x23C, 0x62C), - MX51_PIN_UART3_RXD = _MXC_BUILD_GPIO_PIN(0, 22, 3, 0x240, 0x630), - MX51_PIN_UART3_TXD = _MXC_BUILD_GPIO_PIN(0, 23, 3, 0x244, 0x634), - MX51_PIN_OWIRE_LINE = _MXC_BUILD_GPIO_PIN(0, 24, 3, 0x248, 0x638), - MX51_PIN_KEY_ROW0 = _MXC_BUILD_NON_GPIO_PIN(0x24C, 0x63C), - MX51_PIN_KEY_ROW1 = _MXC_BUILD_NON_GPIO_PIN(0x250, 0x640), - MX51_PIN_KEY_ROW2 = _MXC_BUILD_NON_GPIO_PIN(0x254, 0x644), - MX51_PIN_KEY_ROW3 = _MXC_BUILD_NON_GPIO_PIN(0x258, 0x648), - MX51_PIN_KEY_COL0 = _MXC_BUILD_NON_GPIO_PIN(0x25C, 0x64C), - MX51_PIN_KEY_COL1 = _MXC_BUILD_NON_GPIO_PIN(0x260, 0x650), - MX51_PIN_KEY_COL2 = _MXC_BUILD_NON_GPIO_PIN(0x264, 0x654), - MX51_PIN_KEY_COL3 = _MXC_BUILD_NON_GPIO_PIN(0x268, 0x658), - MX51_PIN_KEY_COL4 = _MXC_BUILD_NON_GPIO_PIN(0x26C, 0x65C), - MX51_PIN_KEY_COL5 = _MXC_BUILD_NON_GPIO_PIN(0x270, 0x660), - MX51_PIN_USBH1_CLK = _MXC_BUILD_GPIO_PIN(0, 25, 2, 0x278, 0x678), - MX51_PIN_USBH1_DIR = _MXC_BUILD_GPIO_PIN(0, 26, 2, 0x27C, 0x67C), - MX51_PIN_USBH1_STP = _MXC_BUILD_GPIO_PIN(0, 27, 2, 0x280, 0x680), - MX51_PIN_USBH1_NXT = _MXC_BUILD_GPIO_PIN(0, 28, 2, 0x284, 0x684), - MX51_PIN_USBH1_DATA0 = _MXC_BUILD_GPIO_PIN(0, 11, 2, 0x288, 0x688), - MX51_PIN_USBH1_DATA1 = _MXC_BUILD_GPIO_PIN(0, 12, 2, 0x28C, 0x68C), - MX51_PIN_USBH1_DATA2 = _MXC_BUILD_GPIO_PIN(0, 13, 2, 0x290, 0x690), - MX51_PIN_USBH1_DATA3 = _MXC_BUILD_GPIO_PIN(0, 14, 2, 0x294, 0x694), - MX51_PIN_USBH1_DATA4 = _MXC_BUILD_GPIO_PIN(0, 15, 2, 0x298, 0x698), - MX51_PIN_USBH1_DATA5 = _MXC_BUILD_GPIO_PIN(0, 16, 2, 0x29C, 0x69C), - MX51_PIN_USBH1_DATA6 = _MXC_BUILD_GPIO_PIN(0, 17, 2, 0x2A0, 0x6A0), - MX51_PIN_USBH1_DATA7 = _MXC_BUILD_GPIO_PIN(0, 18, 2, 0x2A4, 0x6A4), - MX51_PIN_DI1_PIN11 = _MXC_BUILD_GPIO_PIN(2, 0, 4, 0x2A8, 0x6A8), - MX51_PIN_DI1_PIN12 = _MXC_BUILD_GPIO_PIN(2, 1, 4, 0x2AC, 0x6AC), - MX51_PIN_DI1_PIN13 = _MXC_BUILD_GPIO_PIN(2, 2, 4, 0x2B0, 0x6B0), - MX51_PIN_DI1_D0_CS = _MXC_BUILD_GPIO_PIN(2, 3, 4, 0x2B4, 0x6B4), - MX51_PIN_DI1_D1_CS = _MXC_BUILD_GPIO_PIN(2, 4, 4, 0x2B8, 0x6B8), - MX51_PIN_DISPB2_SER_DIN = _MXC_BUILD_GPIO_PIN(2, 5, 4, 0x2BC, 0x6BC), - MX51_PIN_DISPB2_SER_DIO = _MXC_BUILD_GPIO_PIN(2, 6, 4, 0x2C0, 0x6C0), - MX51_PIN_DISPB2_SER_CLK = _MXC_BUILD_GPIO_PIN(2, 7, 4, 0x2C4, 0x6C4), - MX51_PIN_DISPB2_SER_RS = _MXC_BUILD_GPIO_PIN(2, 8, 4, 0x2C8, 0x6C8), - MX51_PIN_DISP1_DAT0 = _MXC_BUILD_NON_GPIO_PIN(0x2CC, 0x6CC), - MX51_PIN_DISP1_DAT1 = _MXC_BUILD_NON_GPIO_PIN(0x2D0, 0x6D0), - MX51_PIN_DISP1_DAT2 = _MXC_BUILD_NON_GPIO_PIN(0x2D4, 0x6D4), - MX51_PIN_DISP1_DAT3 = _MXC_BUILD_NON_GPIO_PIN(0x2D8, 0x6D8), - MX51_PIN_DISP1_DAT4 = _MXC_BUILD_NON_GPIO_PIN(0x2DC, 0x6DC), - MX51_PIN_DISP1_DAT5 = _MXC_BUILD_NON_GPIO_PIN(0x2E0, 0x6E0), - MX51_PIN_DISP1_DAT6 = _MXC_BUILD_NON_GPIO_PIN(0x2E4, 0x6E4), - MX51_PIN_DISP1_DAT7 = _MXC_BUILD_NON_GPIO_PIN(0x2E8, 0x6E8), - MX51_PIN_DISP1_DAT8 = _MXC_BUILD_NON_GPIO_PIN(0x2EC, 0x6EC), - MX51_PIN_DISP1_DAT9 = _MXC_BUILD_NON_GPIO_PIN(0x2F0, 0x6F0), - MX51_PIN_DISP1_DAT10 = _MXC_BUILD_NON_GPIO_PIN(0x2F4, 0x6F4), - MX51_PIN_DISP1_DAT11 = _MXC_BUILD_NON_GPIO_PIN(0x2F8, 0x6F8), - MX51_PIN_DISP1_DAT12 = _MXC_BUILD_NON_GPIO_PIN(0x2FC, 0x6FC), - MX51_PIN_DISP1_DAT13 = _MXC_BUILD_NON_GPIO_PIN(0x300, 0x700), - MX51_PIN_DISP1_DAT14 = _MXC_BUILD_NON_GPIO_PIN(0x304, 0x704), - MX51_PIN_DISP1_DAT15 = _MXC_BUILD_NON_GPIO_PIN(0x308, 0x708), - MX51_PIN_DISP1_DAT16 = _MXC_BUILD_NON_GPIO_PIN(0x30C, 0x70C), - MX51_PIN_DISP1_DAT17 = _MXC_BUILD_NON_GPIO_PIN(0x310, 0x710), - MX51_PIN_DISP1_DAT18 = _MXC_BUILD_NON_GPIO_PIN(0x314, 0x714), - MX51_PIN_DISP1_DAT19 = _MXC_BUILD_NON_GPIO_PIN(0x318, 0x718), - MX51_PIN_DISP1_DAT20 = _MXC_BUILD_NON_GPIO_PIN(0x31C, 0x71C), - MX51_PIN_DISP1_DAT21 = _MXC_BUILD_NON_GPIO_PIN(0x320, 0x720), - MX51_PIN_DISP1_DAT22 = _MXC_BUILD_NON_GPIO_PIN(0x324, 0x724), - MX51_PIN_DISP1_DAT23 = _MXC_BUILD_NON_GPIO_PIN(0x328, 0x728), - MX51_PIN_DI1_PIN3 = _MXC_BUILD_NON_GPIO_PIN(0x32C, 0x72C), - MX51_PIN_DI1_PIN2 = _MXC_BUILD_NON_GPIO_PIN(0x330, 0x734), - MX51_PIN_DI_GP1 = _MXC_BUILD_NON_GPIO_PIN(0x334, 0x73C), - MX51_PIN_DI_GP2 = _MXC_BUILD_NON_GPIO_PIN(0x338, 0x740), - MX51_PIN_DI_GP3 = _MXC_BUILD_NON_GPIO_PIN(0x33C, 0x744), - MX51_PIN_DI2_PIN4 = _MXC_BUILD_NON_GPIO_PIN(0x340, 0x748), - MX51_PIN_DI2_PIN2 = _MXC_BUILD_NON_GPIO_PIN(0x344, 0x74C), - MX51_PIN_DI2_PIN3 = _MXC_BUILD_NON_GPIO_PIN(0x348, 0x750), - MX51_PIN_DI2_DISP_CLK = _MXC_BUILD_NON_GPIO_PIN(0x34C, 0x754), - MX51_PIN_DI_GP4 = _MXC_BUILD_NON_GPIO_PIN(0x350, 0x758), - MX51_PIN_DISP2_DAT0 = _MXC_BUILD_NON_GPIO_PIN(0x354, 0x75C), - MX51_PIN_DISP2_DAT1 = _MXC_BUILD_NON_GPIO_PIN(0x358, 0x760), - MX51_PIN_DISP2_DAT2 = _MXC_BUILD_NON_GPIO_PIN(0x35C, 0x764), - MX51_PIN_DISP2_DAT3 = _MXC_BUILD_NON_GPIO_PIN(0x360, 0x768), - MX51_PIN_DISP2_DAT4 = _MXC_BUILD_NON_GPIO_PIN(0x364, 0x76C), - MX51_PIN_DISP2_DAT5 = _MXC_BUILD_NON_GPIO_PIN(0x368, 0x770), - MX51_PIN_DISP2_DAT6 = _MXC_BUILD_GPIO_PIN(0, 19, 5, 0x36C, 0x774), - MX51_PIN_DISP2_DAT7 = _MXC_BUILD_GPIO_PIN(0, 29, 5, 0x370, 0x778), - MX51_PIN_DISP2_DAT8 = _MXC_BUILD_GPIO_PIN(0, 30, 5, 0x374, 0x77C), - MX51_PIN_DISP2_DAT9 = _MXC_BUILD_GPIO_PIN(0, 31, 5, 0x378, 0x780), - MX51_PIN_DISP2_DAT10 = _MXC_BUILD_NON_GPIO_PIN(0x37C, 0x784), - MX51_PIN_DISP2_DAT11 = _MXC_BUILD_NON_GPIO_PIN(0x380, 0x788), - MX51_PIN_DISP2_DAT12 = _MXC_BUILD_NON_GPIO_PIN(0x384, 0x78C), - MX51_PIN_DISP2_DAT13 = _MXC_BUILD_NON_GPIO_PIN(0x388, 0x790), - MX51_PIN_DISP2_DAT14 = _MXC_BUILD_NON_GPIO_PIN(0x38C, 0x794), - MX51_PIN_DISP2_DAT15 = _MXC_BUILD_NON_GPIO_PIN(0x390, 0x798), - MX51_PIN_SD1_CMD = _MXC_BUILD_NON_GPIO_PIN(0x394, 0x79C), - MX51_PIN_SD1_CLK = _MXC_BUILD_NON_GPIO_PIN(0x398, 0x7A0), - MX51_PIN_SD1_DATA0 = _MXC_BUILD_NON_GPIO_PIN(0x39C, 0x7A4), - MX51_PIN_SD1_DATA1 = _MXC_BUILD_NON_GPIO_PIN(0x3A0, 0x7A8), - MX51_PIN_SD1_DATA2 = _MXC_BUILD_NON_GPIO_PIN(0x3A4, 0x7AC), - MX51_PIN_SD1_DATA3 = _MXC_BUILD_NON_GPIO_PIN(0x3A8, 0x7B0), - MX51_PIN_GPIO1_0 = _MXC_BUILD_GPIO_PIN(0, 0, 1, 0x3AC, 0x7B4), - MX51_PIN_GPIO1_1 = _MXC_BUILD_GPIO_PIN(0, 1, 1, 0x3B0, 0x7B8), - MX51_PIN_SD2_CMD = _MXC_BUILD_NON_GPIO_PIN(0x3B4, 0x7BC), - MX51_PIN_SD2_CLK = _MXC_BUILD_NON_GPIO_PIN(0x3B8, 0x7C0), - MX51_PIN_SD2_DATA0 = _MXC_BUILD_NON_GPIO_PIN(0x3BC, 0x7C4), - MX51_PIN_SD2_DATA1 = _MXC_BUILD_NON_GPIO_PIN(0x3C0, 0x7C8), - MX51_PIN_SD2_DATA2 = _MXC_BUILD_NON_GPIO_PIN(0x3C4, 0x7CC), - MX51_PIN_SD2_DATA3 = _MXC_BUILD_NON_GPIO_PIN(0x3C8, 0x7D0), - MX51_PIN_GPIO1_2 = _MXC_BUILD_GPIO_PIN(0, 2, 0, 0x3CC, 0x7D4), - MX51_PIN_GPIO1_3 = _MXC_BUILD_GPIO_PIN(0, 3, 0, 0x3D0, 0x7D8), - MX51_PIN_PMIC_INT_REQ = _MXC_BUILD_NON_GPIO_PIN(0x3D4, 0x7FC), - MX51_PIN_GPIO1_4 = _MXC_BUILD_GPIO_PIN(0, 4, 0, 0x3D8, 0x804), - MX51_PIN_GPIO1_5 = _MXC_BUILD_GPIO_PIN(0, 5, 0, 0x3DC, 0x808), - MX51_PIN_GPIO1_6 = _MXC_BUILD_GPIO_PIN(0, 6, 0, 0x3E0, 0x80C), - MX51_PIN_GPIO1_7 = _MXC_BUILD_GPIO_PIN(0, 7, 0, 0x3E4, 0x810), - MX51_PIN_GPIO1_8 = _MXC_BUILD_GPIO_PIN(0, 8, 0, 0x3E8, 0x814), - MX51_PIN_GPIO1_9 = _MXC_BUILD_GPIO_PIN(0, 9, 0, 0x3EC, 0x818), + MX51_PIN_NANDF_RB5 = _MXC_BUILD_GPIO_PIN_MX51(2, 13, 3, 0x130, 0x5D8), + MX51_PIN_NANDF_RB6 = _MXC_BUILD_GPIO_PIN_MX51(2, 14, 3, 0x134, 0x5DC), + MX51_PIN_NANDF_RB7 = _MXC_BUILD_GPIO_PIN_MX51(2, 15, 3, 0x138, 0x5E0), + MX51_PIN_NANDF_CS0 = _MXC_BUILD_GPIO_PIN_MX51(2, 16, 3, 0x130, 0x518), + MX51_PIN_NANDF_CS1 = _MXC_BUILD_GPIO_PIN_MX51(2, 17, 3, 0x134, 0x51C), + MX51_PIN_NANDF_CS2 = _MXC_BUILD_GPIO_PIN_MX51(2, 18, 3, 0x138, 0x520), + MX51_PIN_NANDF_CS3 = _MXC_BUILD_GPIO_PIN_MX51(2, 19, 3, 0x13C, 0x524), + MX51_PIN_NANDF_CS4 = _MXC_BUILD_GPIO_PIN_MX51(2, 20, 3, 0x140, 0x528), + MX51_PIN_NANDF_CS5 = _MXC_BUILD_GPIO_PIN_MX51(2, 21, 3, 0x144, 0x52C), + MX51_PIN_NANDF_CS6 = _MXC_BUILD_GPIO_PIN_MX51(2, 22, 3, 0x148, 0x530), + MX51_PIN_NANDF_CS7 = _MXC_BUILD_GPIO_PIN_MX51(2, 23, 3, 0x14C, 0x534), + MX51_PIN_NANDF_RDY_INT = _MXC_BUILD_GPIO_PIN_MX51(2, 24, 3, 0x150, 0x538), + MX51_PIN_NANDF_D15 = _MXC_BUILD_GPIO_PIN_MX51(2, 25, 3, 0x154, 0x53C), + MX51_PIN_NANDF_D14 = _MXC_BUILD_GPIO_PIN_MX51(2, 26, 3, 0x158, 0x540), + MX51_PIN_NANDF_D13 = _MXC_BUILD_GPIO_PIN_MX51(2, 27, 3, 0x15C, 0x544), + MX51_PIN_NANDF_D12 = _MXC_BUILD_GPIO_PIN_MX51(2, 28, 3, 0x160, 0x548), + MX51_PIN_NANDF_D11 = _MXC_BUILD_GPIO_PIN_MX51(2, 29, 3, 0x164, 0x54C), + MX51_PIN_NANDF_D10 = _MXC_BUILD_GPIO_PIN_MX51(2, 30, 3, 0x168, 0x550), + MX51_PIN_NANDF_D9 = _MXC_BUILD_GPIO_PIN_MX51(2, 31, 3, 0x16C, 0x554), + MX51_PIN_NANDF_D8 = _MXC_BUILD_GPIO_PIN_MX51(3, 0, 3, 0x170, 0x558), + MX51_PIN_NANDF_D7 = _MXC_BUILD_GPIO_PIN_MX51(3, 1, 3, 0x174, 0x55C), + MX51_PIN_NANDF_D6 = _MXC_BUILD_GPIO_PIN_MX51(3, 2, 3, 0x178, 0x560), + MX51_PIN_NANDF_D5 = _MXC_BUILD_GPIO_PIN_MX51(3, 3, 3, 0x17C, 0x564), + MX51_PIN_NANDF_D4 = _MXC_BUILD_GPIO_PIN_MX51(3, 4, 3, 0x180, 0x568), + MX51_PIN_NANDF_D3 = _MXC_BUILD_GPIO_PIN_MX51(3, 5, 3, 0x184, 0x56C), + MX51_PIN_NANDF_D2 = _MXC_BUILD_GPIO_PIN_MX51(3, 6, 3, 0x188, 0x570), + MX51_PIN_NANDF_D1 = _MXC_BUILD_GPIO_PIN_MX51(3, 7, 3, 0x18C, 0x574), + MX51_PIN_NANDF_D0 = _MXC_BUILD_GPIO_PIN_MX51(3, 8, 3, 0x190, 0x578), + MX51_PIN_CSI1_D8 = _MXC_BUILD_GPIO_PIN_MX51(2, 12, 3, 0x194, 0x57C), + MX51_PIN_CSI1_D9 = _MXC_BUILD_GPIO_PIN_MX51(2, 13, 3, 0x198, 0x580), + MX51_PIN_CSI1_D10 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x19C, 0x584), + MX51_PIN_CSI1_D11 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x1A0, 0x588), + MX51_PIN_CSI1_D12 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x1A4, 0x58C), + MX51_PIN_CSI1_D13 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x1A8, 0x590), + MX51_PIN_CSI1_D14 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x1AC, 0x594), + MX51_PIN_CSI1_D15 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x1B0, 0x598), + MX51_PIN_CSI1_D16 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x1B4, 0x59C), + MX51_PIN_CSI1_D17 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x1B8, 0x5A0), + MX51_PIN_CSI1_D18 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x1BC, 0x5A4), + MX51_PIN_CSI1_D19 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x1C0, 0x5A8), + MX51_PIN_CSI1_VSYNC = _MXC_BUILD_GPIO_PIN_MX51(2, 14, 3, 0x1C4, 0x5AC), + MX51_PIN_CSI1_HSYNC = _MXC_BUILD_GPIO_PIN_MX51(2, 15, 3, 0x1C8, 0x5B0), + MX51_PIN_CSI1_PIXCLK = _MXC_BUILD_NON_GPIO_PIN_MX51(NON_MUX_I, 0x5B4), + MX51_PIN_CSI1_MCLK = _MXC_BUILD_NON_GPIO_PIN_MX51(NON_MUX_I, 0x5B8), + MX51_PIN_CSI1_PKE0 = _MXC_BUILD_NON_GPIO_PIN_MX51(NON_MUX_I, 0x860), + MX51_PIN_CSI2_D12 = _MXC_BUILD_GPIO_PIN_MX51(3, 9, 3, 0x1CC, 0x5BC), + MX51_PIN_CSI2_D13 = _MXC_BUILD_GPIO_PIN_MX51(3, 10, 3, 0x1D0, 0x5C0), + MX51_PIN_CSI2_D14 = _MXC_BUILD_GPIO_PIN_MX51(3, 11, 3, 0x1D4, 0x5C4), + MX51_PIN_CSI2_D15 = _MXC_BUILD_GPIO_PIN_MX51(3, 12, 3, 0x1D8, 0x5C8), + MX51_PIN_CSI2_D16 = _MXC_BUILD_GPIO_PIN_MX51(3, 11, 3, 0x1DC, 0x5CC), + MX51_PIN_CSI2_D17 = _MXC_BUILD_GPIO_PIN_MX51(3, 12, 3, 0x1E0, 0x5D0), + MX51_PIN_CSI2_D18 = _MXC_BUILD_GPIO_PIN_MX51(3, 11, 3, 0x1E4, 0x5D4), + MX51_PIN_CSI2_D19 = _MXC_BUILD_GPIO_PIN_MX51(3, 12, 3, 0x1E8, 0x5D8), + MX51_PIN_CSI2_VSYNC = _MXC_BUILD_GPIO_PIN_MX51(3, 13, 3, 0x1EC, 0x5DC), + MX51_PIN_CSI2_HSYNC = _MXC_BUILD_GPIO_PIN_MX51(3, 14, 3, 0x1F0, 0x5E0), + MX51_PIN_CSI2_PIXCLK = _MXC_BUILD_GPIO_PIN_MX51(3, 15, 3, 0x1F4, 0x5E4), + MX51_PIN_CSI2_PKE0 = _MXC_BUILD_NON_GPIO_PIN_MX51(NON_MUX_I, 0x81C), + MX51_PIN_I2C1_CLK = _MXC_BUILD_GPIO_PIN_MX51(3, 16, 3, 0x1F8, 0x5E8), + MX51_PIN_I2C1_DAT = _MXC_BUILD_GPIO_PIN_MX51(3, 17, 3, 0x1FC, 0x5EC), + MX51_PIN_AUD3_BB_TXD = _MXC_BUILD_GPIO_PIN_MX51(3, 18, 3, 0x200, 0x5F0), + MX51_PIN_AUD3_BB_RXD = _MXC_BUILD_GPIO_PIN_MX51(3, 19, 3, 0x204, 0x5F4), + MX51_PIN_AUD3_BB_CK = _MXC_BUILD_GPIO_PIN_MX51(3, 20, 3, 0x208, 0x5F8), + MX51_PIN_AUD3_BB_FS = _MXC_BUILD_GPIO_PIN_MX51(3, 21, 3, 0x20C, 0x5FC), + MX51_PIN_CSPI1_MOSI = _MXC_BUILD_GPIO_PIN_MX51(3, 22, 3, 0x210, 0x600), + MX51_PIN_CSPI1_MISO = _MXC_BUILD_GPIO_PIN_MX51(3, 23, 3, 0x214, 0x604), + MX51_PIN_CSPI1_SS0 = _MXC_BUILD_GPIO_PIN_MX51(3, 24, 3, 0x218, 0x608), + MX51_PIN_CSPI1_SS1 = _MXC_BUILD_GPIO_PIN_MX51(3, 25, 3, 0x21C, 0x60C), + MX51_PIN_CSPI1_RDY = _MXC_BUILD_GPIO_PIN_MX51(3, 26, 3, 0x220, 0x610), + MX51_PIN_CSPI1_SCLK = _MXC_BUILD_GPIO_PIN_MX51(3, 27, 3, 0x224, 0x614), + MX51_PIN_UART1_RXD = _MXC_BUILD_GPIO_PIN_MX51(3, 28, 3, 0x228, 0x618), + MX51_PIN_UART1_TXD = _MXC_BUILD_GPIO_PIN_MX51(3, 29, 3, 0x22C, 0x61C), + MX51_PIN_UART1_RTS = _MXC_BUILD_GPIO_PIN_MX51(3, 30, 3, 0x230, 0x620), + MX51_PIN_UART1_CTS = _MXC_BUILD_GPIO_PIN_MX51(3, 31, 3, 0x234, 0x624), + MX51_PIN_UART2_RXD = _MXC_BUILD_GPIO_PIN_MX51(0, 20, 3, 0x238, 0x628), + MX51_PIN_UART2_TXD = _MXC_BUILD_GPIO_PIN_MX51(0, 21, 3, 0x23C, 0x62C), + MX51_PIN_UART3_RXD = _MXC_BUILD_GPIO_PIN_MX51(0, 22, 3, 0x240, 0x630), + MX51_PIN_UART3_TXD = _MXC_BUILD_GPIO_PIN_MX51(0, 23, 3, 0x244, 0x634), + MX51_PIN_OWIRE_LINE = _MXC_BUILD_GPIO_PIN_MX51(0, 24, 3, 0x248, 0x638), + MX51_PIN_KEY_ROW0 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x24C, 0x63C), + MX51_PIN_KEY_ROW1 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x250, 0x640), + MX51_PIN_KEY_ROW2 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x254, 0x644), + MX51_PIN_KEY_ROW3 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x258, 0x648), + MX51_PIN_KEY_COL0 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x25C, 0x64C), + MX51_PIN_KEY_COL1 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x260, 0x650), + MX51_PIN_KEY_COL2 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x264, 0x654), + MX51_PIN_KEY_COL3 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x268, 0x658), + MX51_PIN_KEY_COL4 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x26C, 0x65C), + MX51_PIN_KEY_COL5 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x270, 0x660), + MX51_PIN_USBH1_CLK = _MXC_BUILD_GPIO_PIN_MX51(0, 25, 2, 0x278, 0x678), + MX51_PIN_USBH1_DIR = _MXC_BUILD_GPIO_PIN_MX51(0, 26, 2, 0x27C, 0x67C), + MX51_PIN_USBH1_STP = _MXC_BUILD_GPIO_PIN_MX51(0, 27, 2, 0x280, 0x680), + MX51_PIN_USBH1_NXT = _MXC_BUILD_GPIO_PIN_MX51(0, 28, 2, 0x284, 0x684), + MX51_PIN_USBH1_DATA0 = _MXC_BUILD_GPIO_PIN_MX51(0, 11, 2, 0x288, 0x688), + MX51_PIN_USBH1_DATA1 = _MXC_BUILD_GPIO_PIN_MX51(0, 12, 2, 0x28C, 0x68C), + MX51_PIN_USBH1_DATA2 = _MXC_BUILD_GPIO_PIN_MX51(0, 13, 2, 0x290, 0x690), + MX51_PIN_USBH1_DATA3 = _MXC_BUILD_GPIO_PIN_MX51(0, 14, 2, 0x294, 0x694), + MX51_PIN_USBH1_DATA4 = _MXC_BUILD_GPIO_PIN_MX51(0, 15, 2, 0x298, 0x698), + MX51_PIN_USBH1_DATA5 = _MXC_BUILD_GPIO_PIN_MX51(0, 16, 2, 0x29C, 0x69C), + MX51_PIN_USBH1_DATA6 = _MXC_BUILD_GPIO_PIN_MX51(0, 17, 2, 0x2A0, 0x6A0), + MX51_PIN_USBH1_DATA7 = _MXC_BUILD_GPIO_PIN_MX51(0, 18, 2, 0x2A4, 0x6A4), + MX51_PIN_DI1_PIN11 = _MXC_BUILD_GPIO_PIN_MX51(2, 0, 4, 0x2A8, 0x6A8), + MX51_PIN_DI1_PIN12 = _MXC_BUILD_GPIO_PIN_MX51(2, 1, 4, 0x2AC, 0x6AC), + MX51_PIN_DI1_PIN13 = _MXC_BUILD_GPIO_PIN_MX51(2, 2, 4, 0x2B0, 0x6B0), + MX51_PIN_DI1_D0_CS = _MXC_BUILD_GPIO_PIN_MX51(2, 3, 4, 0x2B4, 0x6B4), + MX51_PIN_DI1_D1_CS = _MXC_BUILD_GPIO_PIN_MX51(2, 4, 4, 0x2B8, 0x6B8), + MX51_PIN_DISPB2_SER_DIN = _MXC_BUILD_GPIO_PIN_MX51(2, 5, 4, 0x2BC, 0x6BC), + MX51_PIN_DISPB2_SER_DIO = _MXC_BUILD_GPIO_PIN_MX51(2, 6, 4, 0x2C0, 0x6C0), + MX51_PIN_DISPB2_SER_CLK = _MXC_BUILD_GPIO_PIN_MX51(2, 7, 4, 0x2C4, 0x6C4), + MX51_PIN_DISPB2_SER_RS = _MXC_BUILD_GPIO_PIN_MX51(2, 8, 4, 0x2C8, 0x6C8), + MX51_PIN_DISP1_DAT0 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x2CC, 0x6CC), + MX51_PIN_DISP1_DAT1 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x2D0, 0x6D0), + MX51_PIN_DISP1_DAT2 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x2D4, 0x6D4), + MX51_PIN_DISP1_DAT3 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x2D8, 0x6D8), + MX51_PIN_DISP1_DAT4 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x2DC, 0x6DC), + MX51_PIN_DISP1_DAT5 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x2E0, 0x6E0), + MX51_PIN_DISP1_DAT6 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x2E4, 0x6E4), + MX51_PIN_DISP1_DAT7 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x2E8, 0x6E8), + MX51_PIN_DISP1_DAT8 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x2EC, 0x6EC), + MX51_PIN_DISP1_DAT9 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x2F0, 0x6F0), + MX51_PIN_DISP1_DAT10 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x2F4, 0x6F4), + MX51_PIN_DISP1_DAT11 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x2F8, 0x6F8), + MX51_PIN_DISP1_DAT12 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x2FC, 0x6FC), + MX51_PIN_DISP1_DAT13 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x300, 0x700), + MX51_PIN_DISP1_DAT14 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x304, 0x704), + MX51_PIN_DISP1_DAT15 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x308, 0x708), + MX51_PIN_DISP1_DAT16 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x30C, 0x70C), + MX51_PIN_DISP1_DAT17 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x310, 0x710), + MX51_PIN_DISP1_DAT18 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x314, 0x714), + MX51_PIN_DISP1_DAT19 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x318, 0x718), + MX51_PIN_DISP1_DAT20 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x31C, 0x71C), + MX51_PIN_DISP1_DAT21 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x320, 0x720), + MX51_PIN_DISP1_DAT22 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x324, 0x724), + MX51_PIN_DISP1_DAT23 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x328, 0x728), + MX51_PIN_DI1_PIN3 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x32C, 0x72C), + MX51_PIN_DI1_PIN2 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x330, 0x734), + MX51_PIN_DI_GP1 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x334, 0x73C), + MX51_PIN_DI_GP2 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x338, 0x740), + MX51_PIN_DI_GP3 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x33C, 0x744), + MX51_PIN_DI2_PIN4 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x340, 0x748), + MX51_PIN_DI2_PIN2 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x344, 0x74C), + MX51_PIN_DI2_PIN3 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x348, 0x750), + MX51_PIN_DI2_DISP_CLK = _MXC_BUILD_NON_GPIO_PIN_MX51(0x34C, 0x754), + MX51_PIN_DI_GP4 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x350, 0x758), + MX51_PIN_DISP2_DAT0 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x354, 0x75C), + MX51_PIN_DISP2_DAT1 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x358, 0x760), + MX51_PIN_DISP2_DAT2 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x35C, 0x764), + MX51_PIN_DISP2_DAT3 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x360, 0x768), + MX51_PIN_DISP2_DAT4 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x364, 0x76C), + MX51_PIN_DISP2_DAT5 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x368, 0x770), + MX51_PIN_DISP2_DAT6 = _MXC_BUILD_GPIO_PIN_MX51(0, 19, 5, 0x36C, 0x774), + MX51_PIN_DISP2_DAT7 = _MXC_BUILD_GPIO_PIN_MX51(0, 29, 5, 0x370, 0x778), + MX51_PIN_DISP2_DAT8 = _MXC_BUILD_GPIO_PIN_MX51(0, 30, 5, 0x374, 0x77C), + MX51_PIN_DISP2_DAT9 = _MXC_BUILD_GPIO_PIN_MX51(0, 31, 5, 0x378, 0x780), + MX51_PIN_DISP2_DAT10 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x37C, 0x784), + MX51_PIN_DISP2_DAT11 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x380, 0x788), + MX51_PIN_DISP2_DAT12 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x384, 0x78C), + MX51_PIN_DISP2_DAT13 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x388, 0x790), + MX51_PIN_DISP2_DAT14 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x38C, 0x794), + MX51_PIN_DISP2_DAT15 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x390, 0x798), + MX51_PIN_SD1_CMD = _MXC_BUILD_NON_GPIO_PIN_MX51(0x394, 0x79C), + MX51_PIN_SD1_CLK = _MXC_BUILD_NON_GPIO_PIN_MX51(0x398, 0x7A0), + MX51_PIN_SD1_DATA0 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x39C, 0x7A4), + MX51_PIN_SD1_DATA1 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x3A0, 0x7A8), + MX51_PIN_SD1_DATA2 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x3A4, 0x7AC), + MX51_PIN_SD1_DATA3 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x3A8, 0x7B0), + MX51_PIN_GPIO1_0 = _MXC_BUILD_GPIO_PIN_MX51(0, 0, 1, 0x3AC, 0x7B4), + MX51_PIN_GPIO1_1 = _MXC_BUILD_GPIO_PIN_MX51(0, 1, 1, 0x3B0, 0x7B8), + MX51_PIN_SD2_CMD = _MXC_BUILD_NON_GPIO_PIN_MX51(0x3B4, 0x7BC), + MX51_PIN_SD2_CLK = _MXC_BUILD_NON_GPIO_PIN_MX51(0x3B8, 0x7C0), + MX51_PIN_SD2_DATA0 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x3BC, 0x7C4), + MX51_PIN_SD2_DATA1 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x3C0, 0x7C8), + MX51_PIN_SD2_DATA2 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x3C4, 0x7CC), + MX51_PIN_SD2_DATA3 = _MXC_BUILD_NON_GPIO_PIN_MX51(0x3C8, 0x7D0), + MX51_PIN_GPIO1_2 = _MXC_BUILD_GPIO_PIN_MX51(0, 2, 0, 0x3CC, 0x7D4), + MX51_PIN_GPIO1_3 = _MXC_BUILD_GPIO_PIN_MX51(0, 3, 0, 0x3D0, 0x7D8), + MX51_PIN_PMIC_INT_REQ = _MXC_BUILD_NON_GPIO_PIN_MX51(0x3D4, 0x7FC), + MX51_PIN_GPIO1_4 = _MXC_BUILD_GPIO_PIN_MX51(0, 4, 0, 0x3D8, 0x804), + MX51_PIN_GPIO1_5 = _MXC_BUILD_GPIO_PIN_MX51(0, 5, 0, 0x3DC, 0x808), + MX51_PIN_GPIO1_6 = _MXC_BUILD_GPIO_PIN_MX51(0, 6, 0, 0x3E0, 0x80C), + MX51_PIN_GPIO1_7 = _MXC_BUILD_GPIO_PIN_MX51(0, 7, 0, 0x3E4, 0x810), + MX51_PIN_GPIO1_8 = _MXC_BUILD_GPIO_PIN_MX51(0, 8, 0, 0x3E8, 0x814), + MX51_PIN_GPIO1_9 = _MXC_BUILD_GPIO_PIN_MX51(0, 9, 0, 0x3EC, 0x818), +}; + +/*! + * various IOMUX input select register index + */ +enum iomux_input_select_mx51 { + MUX_IN_AUDMUX_P4_INPUT_DA_AMX_SELECT_I = 0, + MUX_IN_AUDMUX_P4_INPUT_DB_AMX_SELECT_I, + MUX_IN_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P5_INPUT_DB_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P5_INPUT_RXFS_AMX_SELECT, + MUX_IN_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P6_INPUT_DA_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P6_INPUT_DB_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P6_INPUT_RXCLK_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P6_INPUT_RXFS_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P6_INPUT_TXCLK_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P6_INPUT_TXFS_AMX_SELECT_INPUT, + MUX_IN_CCM_IPP_DI_CLK_SELECT_INPUT, + /* TO2 */ + MUX_IN_CCM_IPP_DI1_CLK_SELECT_INPUT, + MUX_IN_CCM_PLL1_BYPASS_CLK_SELECT_INPUT, + MUX_IN_CCM_PLL2_BYPASS_CLK_SELECT_INPUT, + MUX_IN_CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT, + MUX_IN_CSPI_IPP_IND_MISO_SELECT_INPUT, + MUX_IN_CSPI_IPP_IND_MOSI_SELECT_INPUT, + MUX_IN_CSPI_IPP_IND_SS_B_1_SELECT_INPUT, + MUX_IN_CSPI_IPP_IND_SS_B_2_SELECT_INPUT, + MUX_IN_CSPI_IPP_IND_SS_B_3_SELECT_INPUT, + MUX_IN_DPLLIP1_L1T_TOG_EN_SELECT_INPUT, + /* TO2 */ + MUX_IN_ECSPI2_IPP_IND_SS_B_1_SELECT_INPUT, + MUX_IN_ECSPI2_IPP_IND_SS_B_3_SELECT_INPUT, + MUX_IN_EMI_IPP_IND_RDY_INT_SELECT_INPUT, + MUX_IN_ESDHC3_IPP_DAT0_IN_SELECT_INPUT, + MUX_IN_ESDHC3_IPP_DAT1_IN_SELECT_INPUT, + MUX_IN_ESDHC3_IPP_DAT2_IN_SELECT_INPUT, + MUX_IN_ESDHC3_IPP_DAT3_IN_SELECT_INPUT, + MUX_IN_FEC_FEC_COL_SELECT_INPUT, + MUX_IN_FEC_FEC_CRS_SELECT_INPUT, + MUX_IN_FEC_FEC_MDI_SELECT_INPUT, + MUX_IN_FEC_FEC_RDATA_0_SELECT_INPUT, + MUX_IN_FEC_FEC_RDATA_1_SELECT_INPUT, + MUX_IN_FEC_FEC_RDATA_2_SELECT_INPUT, + MUX_IN_FEC_FEC_RDATA_3_SELECT_INPUT, + MUX_IN_FEC_FEC_RX_CLK_SELECT_INPUT, + MUX_IN_FEC_FEC_RX_DV_SELECT_INPUT, + MUX_IN_FEC_FEC_RX_ER_SELECT_INPUT, + MUX_IN_FEC_FEC_TX_CLK_SELECT_INPUT, + MUX_IN_GPIO3_IPP_IND_G_IN_1_SELECT_INPUT, + MUX_IN_GPIO3_IPP_IND_G_IN_2_SELECT_INPUT, + MUX_IN_GPIO3_IPP_IND_G_IN_3_SELECT_INPUT, + MUX_IN_GPIO3_IPP_IND_G_IN_4_SELECT_INPUT, + MUX_IN_GPIO3_IPP_IND_G_IN_5_SELECT_INPUT, + MUX_IN_GPIO3_IPP_IND_G_IN_6_SELECT_INPUT, + MUX_IN_GPIO3_IPP_IND_G_IN_7_SELECT_INPUT, + MUX_IN_GPIO3_IPP_IND_G_IN_8_SELECT_INPUT, + /* TO2 */ + MUX_IN_GPIO3_IPP_IND_G_IN_12_SELECT_INPUT, + MUX_IN_HSC_MIPI_MIX_IPP_IND_SENS1_DATA_EN_SELECT_INPUT, + MUX_IN_HSC_MIPI_MIX_IPP_IND_SENS2_DATA_EN_SELECT_INPUT, + /* TO2 */ + MUX_IN_HSC_MIPI_MIX_PAR_VSYNC_SELECT_INPUT, + /* TO2 */ + MUX_IN_HSC_MIPI_MIX_PAR_DI_WAIT_SELECT_INPUT, + MUX_IN_HSC_MIPI_MIX_PAR_SISG_TRIG_SELECT_INPUT, + MUX_IN_I2C1_IPP_SCL_IN_SELECT_INPUT, + MUX_IN_I2C1_IPP_SDA_IN_SELECT_INPUT, + MUX_IN_I2C2_IPP_SCL_IN_SELECT_INPUT, + MUX_IN_I2C2_IPP_SDA_IN_SELECT_INPUT, + + MUX_IN_IPU_IPP_DI_0_IND_DISPB_SD_D_SELECT_INPUT, + + MUX_IN_IPU_IPP_DI_1_IND_DISPB_SD_D_SELECT_INPUT, + + MUX_IN_KPP_IPP_IND_COL_6_SELECT_INPUT, + MUX_IN_KPP_IPP_IND_COL_7_SELECT_INPUT, + MUX_IN_KPP_IPP_IND_ROW_4_SELECT_INPUT, + MUX_IN_KPP_IPP_IND_ROW_5_SELECT_INPUT, + MUX_IN_KPP_IPP_IND_ROW_6_SELECT_INPUT, + MUX_IN_KPP_IPP_IND_ROW_7_SELECT_INPUT, + MUX_IN_UART1_IPP_UART_RTS_B_SELECT_INPUT, + MUX_IN_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, + MUX_IN_UART2_IPP_UART_RTS_B_SELECT_INPUT, + MUX_IN_UART2_IPP_UART_RXD_MUX_SELECT_INPUT, + MUX_IN_UART3_IPP_UART_RTS_B_SELECT_INPUT, + MUX_IN_UART3_IPP_UART_RXD_MUX_SELECT_INPUT, + MUX_IN_USBOH3_IPP_IND_UH3_CLK_SELECT_INPUT, + MUX_IN_USBOH3_IPP_IND_UH3_DATA_0_SELECT_INPUT, + MUX_IN_USBOH3_IPP_IND_UH3_DATA_1_SELECT_INPUT, + MUX_IN_USBOH3_IPP_IND_UH3_DATA_2_SELECT_INPUT, + MUX_IN_USBOH3_IPP_IND_UH3_DATA_3_SELECT_INPUT, + MUX_IN_USBOH3_IPP_IND_UH3_DATA_4_SELECT_INPUT, + MUX_IN_USBOH3_IPP_IND_UH3_DATA_5_SELECT_INPUT, + MUX_IN_USBOH3_IPP_IND_UH3_DATA_6_SELECT_INPUT, + MUX_IN_USBOH3_IPP_IND_UH3_DATA_7_SELECT_INPUT, + MUX_IN_USBOH3_IPP_IND_UH3_DIR_SELECT_INPUT, + MUX_IN_USBOH3_IPP_IND_UH3_NXT_SELECT_INPUT, + MUX_IN_USBOH3_IPP_IND_UH3_STP_SELECT_INPUT, + MUX_INPUT_NUM_MUX, }; #endif /* __ASSEMBLY__ */ diff --git a/arch/arm/mach-mx5/mx53_evk.c b/arch/arm/mach-mx5/mx53_evk.c new file mode 100644 index 000000000000..4b828cdd613d --- /dev/null +++ b/arch/arm/mach-mx5/mx53_evk.c @@ -0,0 +1,598 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <linux/types.h> +#include <linux/sched.h> +#include <linux/delay.h> +#include <linux/pm.h> +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/init.h> +#include <linux/input.h> +#include <linux/nodemask.h> +#include <linux/clk.h> +#include <linux/platform_device.h> +#include <linux/fsl_devices.h> +#include <linux/spi/spi.h> +#include <linux/i2c.h> +#include <linux/ata.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/map.h> +#include <linux/mtd/partitions.h> +#include <linux/spi/flash.h> +#include <linux/regulator/consumer.h> +#include <linux/pmic_external.h> +#include <linux/pmic_status.h> +#include <linux/ipu.h> +#include <linux/mxcfb.h> +#include <linux/pwm_backlight.h> +#include <mach/common.h> +#include <mach/hardware.h> +#include <asm/irq.h> +#include <asm/setup.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/time.h> +#include <asm/mach/keypad.h> +#include <mach/memory.h> +#include <mach/gpio.h> +#include <mach/mmc.h> +#include <mach/mxc_dvfs.h> +#include "board-mx53_evk.h" +#include "iomux.h" +#include "mx53_pins.h" +#include "crm_regs.h" +#include "devices.h" +#include "usb.h" + +/*! + * @file mach-mx53/mx53_evk.c + * + * @brief This file contains the board specific initialization routines. + * + * @ingroup MSL_MX53 + */ +extern void __init mx53_evk_io_init(void); +extern struct cpu_wp *(*get_cpu_wp)(int *wp); +extern void (*set_num_cpu_wp)(int num); +static int num_cpu_wp = 3; + +/* working point(wp): 0 - 800MHz; 1 - 166.25MHz; */ +static struct cpu_wp cpu_wp_auto[] = { + { + .pll_rate = 1000000000, + .cpu_rate = 1000000000, + .pdf = 0, + .mfi = 10, + .mfd = 11, + .mfn = 5, + .cpu_podf = 0, + .cpu_voltage = 1175000,}, + { + .pll_rate = 800000000, + .cpu_rate = 800000000, + .pdf = 0, + .mfi = 8, + .mfd = 2, + .mfn = 1, + .cpu_podf = 0, + .cpu_voltage = 1100000,}, + { + .pll_rate = 800000000, + .cpu_rate = 166250000, + .pdf = 4, + .mfi = 8, + .mfd = 2, + .mfn = 1, + .cpu_podf = 4, + .cpu_voltage = 850000,}, +}; + +static struct fb_videomode video_modes[] = { + { + /* 720p60 TV output */ + "720P60", 60, 1280, 720, 13468, + 260, 109, + 25, 4, + 1, 1, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT | + FB_SYNC_EXT, + FB_VMODE_NONINTERLACED, + 0,}, + { + /* MITSUBISHI LVDS panel */ + "XGA", 60, 1024, 768, 15385, + 220, 40, + 21, 7, + 60, 10, + 0, + FB_VMODE_NONINTERLACED, + 0,}, +}; + +struct cpu_wp *mx53_evk_get_cpu_wp(int *wp) +{ + *wp = num_cpu_wp; + return cpu_wp_auto; +} + +void mx53_evk_set_num_cpu_wp(int num) +{ + num_cpu_wp = num; + return; +} + +static struct mxc_w1_config mxc_w1_data = { + .search_rom_accelerator = 1, +}; + +static struct platform_pwm_backlight_data mxc_pwm_backlight_data = { + .pwm_id = 0, + .max_brightness = 255, + .dft_brightness = 128, + .pwm_period_ns = 78770, +}; + +static struct mxc_ipu_config mxc_ipu_data = { + .rev = 3, +}; + +extern void mx53_evk_gpio_spi_chipselect_active(int cspi_mode, int status, + int chipselect); +extern void mx53_evk_gpio_spi_chipselect_inactive(int cspi_mode, int status, + int chipselect); +static struct mxc_spi_master mxcspi1_data = { + .maxchipselect = 4, + .spi_version = 23, + .chipselect_active = mx53_evk_gpio_spi_chipselect_active, + .chipselect_inactive = mx53_evk_gpio_spi_chipselect_inactive, +}; + +static struct mxc_i2c_platform_data mxci2c_data = { + .i2c_clk = 100000, +}; + +static struct mxc_srtc_platform_data srtc_data = { + .srtc_sec_mode_addr = 0x83F98840, +}; + +static struct tve_platform_data tve_data = { + .dac_reg = "VVIDEO", +}; + +static struct resource mxcfb_resources[] = { + [0] = { + .flags = IORESOURCE_MEM, + }, +}; + +static struct mxc_fb_platform_data fb_data[] = { + { + .interface_pix_fmt = IPU_PIX_FMT_RGB565, + .mode_str = "800x480M-16@55", + }, + { + .interface_pix_fmt = IPU_PIX_FMT_RGB24, + .mode_str = "1024x768M-16@60", + }, +}; + +static int __initdata enable_vga = { 0 }; +static int __initdata enable_tv = { 0 }; + +static void wvga_reset(void) +{ +} + +static struct mxc_lcd_platform_data lcd_wvga_data = { + .reset = wvga_reset, +}; + +static struct platform_device lcd_wvga_device = { + .name = "lcd_claa", +}; + +static int __init mxc_init_fb(void) +{ + if (!machine_is_mx53_evk()) + return 0; + + /* by default, fb0 is wvga, fb1 is vga or tv */ + if (enable_vga) { + printk(KERN_INFO "VGA monitor is primary\n"); + } else if (enable_tv == 2) + printk(KERN_INFO "HDTV is primary\n"); + else + printk(KERN_INFO "WVGA LCD panel is primary\n"); + + if (enable_tv) { + printk(KERN_INFO "HDTV is specified as %d\n", enable_tv); + fb_data[1].interface_pix_fmt = IPU_PIX_FMT_YUV444; + fb_data[1].mode = &(video_modes[0]); + } + + /* Once a customer knows the platform configuration, + this should be simplified to what is desired. + */ + if (enable_vga || enable_tv == 2) { + /* + * DI1 -> DP-BG channel: + * + * dev di-out-fmt default-videmode + * + * 1. VGA RGB 1024x768M-16@60 + * 2. TVE YUV video_modes[0] + */ + mxc_fb_devices[1].num_resources = ARRAY_SIZE(mxcfb_resources); + mxc_fb_devices[1].resource = mxcfb_resources; + mxc_register_device(&mxc_fb_devices[1], &fb_data[1]); + if (fb_data[0].mode_str || fb_data[0].mode) + /* + * DI0 -> DC channel: + * + * dev di-out-fmt default-videmode + * + * 1. WVGA RGB 800x480M-16@55 + */ + mxc_register_device(&mxc_fb_devices[0], &fb_data[0]); + } else { + /* + * DI0 -> DP-BG channel: + * + * dev di-out-fmt default-videmode + * + * 1. WVGA RGB 800x480M-16@55 + */ + mxc_fb_devices[0].num_resources = ARRAY_SIZE(mxcfb_resources); + mxc_fb_devices[0].resource = mxcfb_resources; + mxc_register_device(&mxc_fb_devices[0], &fb_data[0]); + if (fb_data[1].mode_str || fb_data[1].mode) + /* + * DI1 -> DC channel: + * + * dev di-out-fmt default-videmode + * + * 1. VGA RGB 1024x768M-16@60 + * 2. TVE YUV video_modes[0] + */ + mxc_register_device(&mxc_fb_devices[1], &fb_data[1]); + } + + /* + * DI0/1 DP-FG channel: + */ + mxc_register_device(&mxc_fb_devices[2], NULL); + + return 0; +} +device_initcall(mxc_init_fb); + +static int __init vga_setup(char *__unused) +{ + enable_vga = 1; + return 1; +} +__setup("vga", vga_setup); + +static int __init tv_setup(char *s) +{ + enable_tv = 1; + if (strcmp(s, "2") == 0 || strcmp(s, "=2") == 0) + enable_tv = 2; + return 1; +} +__setup("hdtv", tv_setup); + +static struct mxc_camera_platform_data camera_data = { + .io_regulator = "SW4", + .analog_regulator = "VIOHI", + .mclk = 24000000, + .csi = 0, +}; + +static struct i2c_board_info mxc_i2c0_board_info[] __initdata = { + { + .type = "ov3640", + .addr = 0x3C, + .platform_data = (void *)&camera_data, + }, +}; + +/* TO DO add platform data */ +static struct i2c_board_info mxc_i2c1_board_info[] __initdata = { + { + .type = "sgtl5000-i2c", + .addr = 0x0a, + }, + { + .type = "tsc2007", + .addr = 0x48, + .irq = IOMUX_TO_IRQ(MX53_PIN_EIM_A25), + }, + { + .type = "backlight-i2c", + .addr = 0x2c, + }, + { + .type = "vga-ddc", + .addr = 0x1f, + }, + { + .type = "eeprom", + .addr = 0x50, + }, +}; + +static int sdhc_write_protect(struct device *dev) +{ + unsigned short rc = 0; + + if (to_platform_device(dev)->id == 0) + rc = gpio_get_value(IOMUX_TO_GPIO(MX53_PIN_EIM_DA14)); + else if (to_platform_device(dev)->id == 1) + rc = gpio_get_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_2)); + else + rc = gpio_get_value(IOMUX_TO_GPIO(MX53_PIN_EIM_DA12)); + + return rc; +} + +static unsigned int sdhc_get_card_det_status(struct device *dev) +{ + int ret; + + if (to_platform_device(dev)->id == 0) { + ret = gpio_get_value(IOMUX_TO_GPIO(MX53_PIN_EIM_DA13)); + } else if (to_platform_device(dev)->id == 1) { + ret = gpio_get_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_4)); + } else{ /* config the det pin for SDHC3 */ + ret = gpio_get_value(IOMUX_TO_GPIO(MX53_PIN_EIM_DA11)); + } + + return ret; +} + +static struct mxc_mmc_platform_data mmc1_data = { + .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 + | MMC_VDD_31_32, + .caps = MMC_CAP_4_BIT_DATA, + .min_clk = 400000, + .max_clk = 50000000, + .card_inserted_state = 0, + .status = sdhc_get_card_det_status, + .wp_status = sdhc_write_protect, + .clock_mmc = "esdhc_clk", + .power_mmc = NULL, +}; + +static struct mxc_mmc_platform_data mmc3_data = { + .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 + | MMC_VDD_31_32, + .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, + .min_clk = 400000, + .max_clk = 50000000, + .card_inserted_state = 0, + .status = sdhc_get_card_det_status, + .wp_status = sdhc_write_protect, + .clock_mmc = "esdhc_clk", +}; + +static int mxc_sgtl5000_amp_enable(int enable) +{ +/* TO DO */ +return 0; +} + +static int headphone_det_status(void) +{ + return (gpio_get_value(IOMUX_TO_GPIO(MX53_PIN_ATA_DATA5)) == 0); +} + +static int mxc_sgtl5000_init(void); + +static struct mxc_audio_platform_data sgtl5000_data = { + .ssi_num = 1, + .src_port = 2, + .ext_port = 5, + .hp_irq = IOMUX_TO_IRQ(MX53_PIN_ATA_DATA5), + .hp_status = headphone_det_status, + .amp_enable = mxc_sgtl5000_amp_enable, + .init = mxc_sgtl5000_init, +}; + +static int mxc_sgtl5000_init(void) +{ + struct clk *ssi_ext1; + int rate; + + ssi_ext1 = clk_get(NULL, "ssi_ext1_clk"); + if (IS_ERR(ssi_ext1)) + return -1; + + rate = clk_round_rate(ssi_ext1, 12000000); + if (rate < 8000000 || rate > 27000000) { + printk(KERN_ERR "Error: SGTL5000 mclk freq %d out of range!\n", + rate); + clk_put(ssi_ext1); + return -1; + } + + clk_set_rate(ssi_ext1, rate); + clk_enable(ssi_ext1); + sgtl5000_data.sysclk = rate; + + return 0; +} + +static struct platform_device mxc_sgtl5000_device = { + .name = "imx-3stack-sgtl5000", +}; + +/*! + * Board specific fixup function. It is called by \b setup_arch() in + * setup.c file very early on during kernel starts. It allows the user to + * statically fill in the proper values for the passed-in parameters. None of + * the parameters is used currently. + * + * @param desc pointer to \b struct \b machine_desc + * @param tags pointer to \b struct \b tag + * @param cmdline pointer to the command line + * @param mi pointer to \b struct \b meminfo + */ +static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags, + char **cmdline, struct meminfo *mi) +{ + char *str; + int size = 0; + unsigned long orig_size; + struct tag *t; + + mxc_set_cpu_type(MXC_CPU_MX53); + + get_cpu_wp = mx53_evk_get_cpu_wp; + set_num_cpu_wp = mx53_evk_set_num_cpu_wp; + + for_each_tag(t, tags) { + if (t->hdr.tag != ATAG_CMDLINE) + continue; + str = t->u.cmdline.cmdline; + str = strstr(str, "mem="); + if (str != NULL) { + str += 4; + size = memparse(str, &str); + if (size == 0 || size == SZ_512M) + return; + } + } + + for_each_tag(t, tags) { + if (t->hdr.tag != ATAG_MEM) + continue; + + orig_size = t->u.mem.size; + if (!size) + size = t->u.mem.size - SZ_32M; + t->u.mem.size = size; +#if defined(CONFIG_FB_MXC_SYNC_PANEL) || \ + defined(CONFIG_FB_MXC_SYNC_PANEL_MODULE) + mxcfb_resources[0].start = t->u.mem.start + size; + mxcfb_resources[0].end = t->u.mem.start + orig_size - 1; + break; +#endif + } +} + +/*! + * Board specific initialization. + */ +static void __init mxc_board_init(void) +{ + mxc_ipu_data.di_clk[0] = clk_get(NULL, "ipu_di0_clk"); + mxc_ipu_data.di_clk[1] = clk_get(NULL, "ipu_di1_clk"); + + /* SD card detect irqs */ + mxcsdhc3_device.resource[2].start = IOMUX_TO_IRQ(MX53_PIN_EIM_DA11); + mxcsdhc3_device.resource[2].end = IOMUX_TO_IRQ(MX53_PIN_EIM_DA11); + mxcsdhc1_device.resource[2].start = IOMUX_TO_IRQ(MX53_PIN_EIM_DA13); + mxcsdhc1_device.resource[2].end = IOMUX_TO_IRQ(MX53_PIN_EIM_DA13); + + mxc_cpu_common_init(); + mxc_register_gpios(); + mx53_evk_io_init(); + + mxc_register_device(&mxc_dma_device, NULL); + mxc_register_device(&mxc_wdt_device, NULL); + mxc_register_device(&mxcspi1_device, &mxcspi1_data); + mxc_register_device(&mxci2c_devices[0], &mxci2c_data); + mxc_register_device(&mxci2c_devices[1], &mxci2c_data); + mxc_register_device(&mxci2c_devices[2], &mxci2c_data); + + mxc_register_device(&mxc_rtc_device, &srtc_data); + mxc_register_device(&mxc_w1_master_device, &mxc_w1_data); + mxc_register_device(&mxc_ipu_device, &mxc_ipu_data); + mxc_register_device(&lcd_wvga_device, &lcd_wvga_data); + mxc_register_device(&mxc_tve_device, &tve_data); + mxc_register_device(&mxcvpu_device, NULL); + mxc_register_device(&gpu_device, NULL); + /* + mxc_register_device(&mx53_lpmode_device, NULL); + mxc_register_device(&busfreq_device, NULL); + mxc_register_device(&sdram_autogating_device, NULL); + mxc_register_device(&mxc_dvfs_core_device, &dvfs_core_data); + mxc_register_device(&mxc_dvfs_per_device, &dvfs_per_data); + */ + mxc_register_device(&mxc_iim_device, NULL); + mxc_register_device(&mxc_pwm1_device, NULL); + mxc_register_device(&mxc_pwm_backlight_device, &mxc_pwm_backlight_data); +/* mxc_register_device(&mxc_keypad_device, &keypad_plat_data); */ + + mxc_register_device(&mxcsdhc1_device, &mmc1_data); + mxc_register_device(&mxcsdhc3_device, &mmc3_data); + mxc_register_device(&mxc_ssi1_device, NULL); + mxc_register_device(&mxc_ssi2_device, NULL); + /* + mxc_register_device(&mxc_alsa_spdif_device, &mxc_spdif_data); + */ + mxc_register_device(&mxc_fec_device, NULL); + +/* + spi_register_board_info(mxc_spi_nor_device, + ARRAY_SIZE(mxc_spi_nor_device)); +*/ + + i2c_register_board_info(0, mxc_i2c0_board_info, + ARRAY_SIZE(mxc_i2c0_board_info)); + i2c_register_board_info(1, mxc_i2c1_board_info, + ARRAY_SIZE(mxc_i2c1_board_info)); + + mx53_evk_init_mc13892(); +/* + pm_power_off = mxc_power_off; + */ + + mxc_register_device(&mxc_sgtl5000_device, &sgtl5000_data); +} + +static void __init mx53_evk_timer_init(void) +{ + struct clk *uart_clk; + + mx53_clocks_init(32768, 24000000, 22579200, 24576000); + + uart_clk = clk_get(NULL, "uart_clk.0"); + early_console_setup(MX53_BASE_ADDR(UART1_BASE_ADDR), uart_clk); +} + +static struct sys_timer mxc_timer = { + .init = mx53_evk_timer_init, +}; + +/* + * The following uses standard kernel macros define in arch.h in order to + * initialize __mach_desc_MX53_EVK data structure. + */ +MACHINE_START(MX53_EVK, "Freescale MX53 EVK Board") + /* Maintainer: Freescale Semiconductor, Inc. */ + .fixup = fixup_mxc_board, + .map_io = mx5_map_io, + .init_irq = mx5_init_irq, + .init_machine = mxc_board_init, + .timer = &mxc_timer, +MACHINE_END diff --git a/arch/arm/mach-mx5/mx53_evk_gpio.c b/arch/arm/mach-mx5/mx53_evk_gpio.c new file mode 100644 index 000000000000..f5cb20d67bfb --- /dev/null +++ b/arch/arm/mach-mx5/mx53_evk_gpio.c @@ -0,0 +1,749 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <linux/errno.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/delay.h> +#include <linux/io.h> +#include <mach/hardware.h> +#include <mach/gpio.h> + +#include "iomux.h" +#include "mx53_pins.h" + +/*! + * @file mach-mx53/mx53_evk_gpio.c + * + * @brief This file contains all the GPIO setup functions for the board. + * + * @ingroup GPIO + */ + +static struct mxc_iomux_pin_cfg __initdata mxc_iomux_pins[] = { + { + MX53_PIN_EIM_WAIT, IOMUX_CONFIG_ALT1, + }, + { + MX53_PIN_EIM_OE, IOMUX_CONFIG_ALT3, + }, + { + MX53_PIN_EIM_RW, IOMUX_CONFIG_ALT3, + }, + { + MX53_PIN_EIM_A23, IOMUX_CONFIG_GPIO, + }, + { + MX53_PIN_EIM_A24, IOMUX_CONFIG_GPIO, + }, + { + MX53_PIN_EIM_A25, IOMUX_CONFIG_ALT6, + }, + { + MX53_PIN_EIM_D16, IOMUX_CONFIG_ALT4, + }, + { + MX53_PIN_EIM_D17, IOMUX_CONFIG_ALT4, + }, + { + MX53_PIN_EIM_D18, IOMUX_CONFIG_ALT2, + }, + { + MX53_PIN_EIM_D19, IOMUX_CONFIG_ALT2, + }, + { + MX53_PIN_EIM_D20, IOMUX_CONFIG_ALT3, + }, + { + MX53_PIN_EIM_D21, IOMUX_CONFIG_ALT3, + }, + { + MX53_PIN_EIM_D22, IOMUX_CONFIG_ALT3, + }, + { + MX53_PIN_EIM_D23, IOMUX_CONFIG_ALT4, + }, + { + MX53_PIN_EIM_D24, IOMUX_CONFIG_GPIO, + }, + { + MX53_PIN_EIM_D25, IOMUX_CONFIG_GPIO, + }, + { + MX53_PIN_EIM_D26, IOMUX_CONFIG_GPIO, + }, + { + MX53_PIN_EIM_D28, IOMUX_CONFIG_ALT3, + }, + { + MX53_PIN_EIM_D29, IOMUX_CONFIG_ALT3, + }, + { + MX53_PIN_EIM_D30, IOMUX_CONFIG_ALT4, + }, + { + MX53_PIN_EIM_D31, IOMUX_CONFIG_ALT4, + }, + { + MX53_PIN_EIM_DA11, IOMUX_CONFIG_GPIO, + }, + { + MX53_PIN_EIM_DA12, IOMUX_CONFIG_GPIO, + }, + { + MX53_PIN_EIM_DA13, IOMUX_CONFIG_GPIO, + }, + { + MX53_PIN_EIM_DA14, IOMUX_CONFIG_GPIO, + }, + { + MX53_PIN_EIM_DA15, IOMUX_CONFIG_GPIO, + }, + { + MX53_PIN_NANDF_CS2, IOMUX_CONFIG_ALT3, + }, + { + MX53_PIN_NANDF_CS3, IOMUX_CONFIG_ALT3, + }, + { + MX53_PIN_ATA_BUFFER_EN, IOMUX_CONFIG_ALT3, + }, + { + MX53_PIN_ATA_CS_0, IOMUX_CONFIG_ALT4, + }, + { + MX53_PIN_ATA_CS_1, IOMUX_CONFIG_ALT4, + }, + { + MX53_PIN_ATA_DA_1, IOMUX_CONFIG_GPIO, + }, + { + MX53_PIN_ATA_DA_2, IOMUX_CONFIG_GPIO, + }, + { + MX53_PIN_ATA_DATA4, IOMUX_CONFIG_GPIO, + }, + { + MX53_PIN_ATA_DATA6, IOMUX_CONFIG_GPIO, + }, + { + MX53_PIN_ATA_DATA7, IOMUX_CONFIG_GPIO, + }, + { + MX53_PIN_ATA_DATA12, IOMUX_CONFIG_ALT2, + }, + { + MX53_PIN_ATA_DATA13, IOMUX_CONFIG_ALT2, + }, + { + MX53_PIN_ATA_DATA14, IOMUX_CONFIG_ALT2, + }, + { + MX53_PIN_ATA_DATA15, IOMUX_CONFIG_ALT2, + }, + { + MX53_PIN_ATA_DIOR, IOMUX_CONFIG_ALT3, + }, + { + MX53_PIN_ATA_DIOW, IOMUX_CONFIG_ALT3, + }, + { + MX53_PIN_ATA_DMACK, IOMUX_CONFIG_ALT3, + }, + { + MX53_PIN_ATA_DMARQ, IOMUX_CONFIG_ALT3, + }, + { + MX53_PIN_ATA_INTRQ, IOMUX_CONFIG_ALT3, + }, + { + MX53_PIN_KEY_COL0, IOMUX_CONFIG_ALT2, + }, + { + MX53_PIN_KEY_ROW0, IOMUX_CONFIG_ALT2, + }, + { + MX53_PIN_KEY_COL1, IOMUX_CONFIG_ALT2, + }, + { + MX53_PIN_KEY_ROW1, IOMUX_CONFIG_ALT2, + }, + { + MX53_PIN_KEY_COL2, IOMUX_CONFIG_ALT2, + }, + { + MX53_PIN_KEY_ROW2, IOMUX_CONFIG_ALT2, + }, + { + MX53_PIN_KEY_COL3, IOMUX_CONFIG_ALT4, + }, + { + MX53_PIN_KEY_COL4, IOMUX_CONFIG_ALT2, + }, + { + MX53_PIN_KEY_ROW4, IOMUX_CONFIG_ALT2, + }, + { + MX53_PIN_CSI0_D4, IOMUX_CONFIG_ALT5, + }, + { + MX53_PIN_CSI0_D5, IOMUX_CONFIG_ALT5, + }, + { + MX53_PIN_CSI0_D6, IOMUX_CONFIG_ALT5, + }, + { + MX53_PIN_CSI0_D7, IOMUX_CONFIG_ALT5, + }, + { + MX53_PIN_CSI0_D9, IOMUX_CONFIG_ALT5, + }, + { /* UART1 Tx */ + MX53_PIN_CSI0_D10, IOMUX_CONFIG_ALT2, + (PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST), + }, + { /* UART1 Rx */ + MX53_PIN_CSI0_D11, IOMUX_CONFIG_ALT2, + (PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST), + MUX_IN_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, + INPUT_CTL_PATH1, + }, + { + MX53_PIN_CSI0_DATA_EN, IOMUX_CONFIG_GPIO, + }, + { + MX53_PIN_GPIO_1, IOMUX_CONFIG_GPIO, + }, + { + MX53_PIN_GPIO_2, IOMUX_CONFIG_GPIO, + }, + { + MX53_PIN_GPIO_3, IOMUX_CONFIG_GPIO, + }, + { + MX53_PIN_GPIO_4, IOMUX_CONFIG_GPIO, + }, + { + MX53_PIN_GPIO_5, IOMUX_CONFIG_GPIO, + }, + { + MX53_PIN_GPIO_6, IOMUX_CONFIG_GPIO, + }, + { + MX53_PIN_GPIO_7, IOMUX_CONFIG_GPIO, + }, + { + MX53_PIN_GPIO_8, IOMUX_CONFIG_GPIO, + }, + { + MX53_PIN_GPIO_10, IOMUX_CONFIG_GPIO, + }, + { + MX53_PIN_GPIO_11, IOMUX_CONFIG_GPIO, + }, + { + MX53_PIN_GPIO_12, IOMUX_CONFIG_GPIO, + }, + { + MX53_PIN_GPIO_13, IOMUX_CONFIG_GPIO, + }, + { + MX53_PIN_GPIO_14, IOMUX_CONFIG_GPIO, + }, + { + MX53_PIN_GPIO_16, IOMUX_CONFIG_ALT1, + }, + { + MX53_PIN_GPIO_17, IOMUX_CONFIG_GPIO, + }, + { + MX53_PIN_GPIO_18, IOMUX_CONFIG_GPIO, + }, + { + MX53_PIN_GPIO_19, IOMUX_CONFIG_ALT3, + }, + { /* DI0 display clock */ + MX53_PIN_DI0_DISP_CLK, IOMUX_CONFIG_ALT0, + (PAD_CTL_HYS_NONE | PAD_CTL_PKE_NONE | PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST), + }, + { /* DI0 data enable */ + MX53_PIN_DI0_PIN15, IOMUX_CONFIG_ALT0, + (PAD_CTL_HYS_NONE | PAD_CTL_PKE_NONE | PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_DRV_LOW | PAD_CTL_SRE_SLOW), + }, + { /* DI0 HSYNC */ + MX53_PIN_DI0_PIN2, IOMUX_CONFIG_ALT0, + (PAD_CTL_HYS_NONE | PAD_CTL_PKE_NONE | PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_DRV_LOW | PAD_CTL_SRE_SLOW), + }, + { /* DI0 VSYNC */ + MX53_PIN_DI0_PIN3, IOMUX_CONFIG_ALT0, + (PAD_CTL_HYS_NONE | PAD_CTL_PKE_NONE | PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_DRV_LOW | PAD_CTL_SRE_SLOW), + }, + { + MX53_PIN_DISP0_DAT0, IOMUX_CONFIG_ALT0, + (PAD_CTL_HYS_NONE | PAD_CTL_PKE_NONE | PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_DRV_LOW | PAD_CTL_SRE_SLOW), + }, + { + MX53_PIN_DISP0_DAT1, IOMUX_CONFIG_ALT0, + (PAD_CTL_HYS_NONE | PAD_CTL_PKE_NONE | PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_DRV_LOW | PAD_CTL_SRE_SLOW), + }, + { + MX53_PIN_DISP0_DAT2, IOMUX_CONFIG_ALT0, + (PAD_CTL_HYS_NONE | PAD_CTL_PKE_NONE | PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_DRV_LOW | PAD_CTL_SRE_SLOW), + }, + { + MX53_PIN_DISP0_DAT3, IOMUX_CONFIG_ALT0, + (PAD_CTL_HYS_NONE | PAD_CTL_PKE_NONE | PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_DRV_LOW | PAD_CTL_SRE_SLOW), + }, + { + MX53_PIN_DISP0_DAT4, IOMUX_CONFIG_ALT0, + (PAD_CTL_HYS_NONE | PAD_CTL_PKE_NONE | PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_DRV_LOW | PAD_CTL_SRE_SLOW), + }, + { + MX53_PIN_DISP0_DAT5, IOMUX_CONFIG_ALT0, + (PAD_CTL_HYS_NONE | PAD_CTL_PKE_NONE | PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_DRV_LOW | PAD_CTL_SRE_SLOW), + }, + { + MX53_PIN_DISP0_DAT6, IOMUX_CONFIG_ALT0, + (PAD_CTL_HYS_NONE | PAD_CTL_PKE_NONE | PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_DRV_LOW | PAD_CTL_SRE_SLOW), + }, + { + MX53_PIN_DISP0_DAT7, IOMUX_CONFIG_ALT0, + (PAD_CTL_HYS_NONE | PAD_CTL_PKE_NONE | PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_DRV_LOW | PAD_CTL_SRE_SLOW), + }, + { + MX53_PIN_DISP0_DAT8, IOMUX_CONFIG_ALT0, + (PAD_CTL_HYS_NONE | PAD_CTL_PKE_NONE | PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_DRV_LOW | PAD_CTL_SRE_SLOW), + }, + { + MX53_PIN_DISP0_DAT9, IOMUX_CONFIG_ALT0, + (PAD_CTL_HYS_NONE | PAD_CTL_PKE_NONE | PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_DRV_LOW | PAD_CTL_SRE_SLOW), + }, + { + MX53_PIN_DISP0_DAT10, IOMUX_CONFIG_ALT0, + (PAD_CTL_HYS_NONE | PAD_CTL_PKE_NONE | PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_DRV_LOW | PAD_CTL_SRE_SLOW), + }, + { + MX53_PIN_DISP0_DAT11, IOMUX_CONFIG_ALT0, + (PAD_CTL_HYS_NONE | PAD_CTL_PKE_NONE | PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_DRV_LOW | PAD_CTL_SRE_SLOW), + }, + { + MX53_PIN_DISP0_DAT12, IOMUX_CONFIG_ALT0, + (PAD_CTL_HYS_NONE | PAD_CTL_PKE_NONE | PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_DRV_LOW | PAD_CTL_SRE_SLOW), + }, + { + MX53_PIN_DISP0_DAT13, IOMUX_CONFIG_ALT0, + (PAD_CTL_HYS_NONE | PAD_CTL_PKE_NONE | PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_DRV_LOW | PAD_CTL_SRE_SLOW), + }, + { + MX53_PIN_DISP0_DAT14, IOMUX_CONFIG_ALT0, + (PAD_CTL_HYS_NONE | PAD_CTL_PKE_NONE | PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_DRV_LOW | PAD_CTL_SRE_SLOW), + }, + { + MX53_PIN_DISP0_DAT15, IOMUX_CONFIG_ALT0, + (PAD_CTL_HYS_NONE | PAD_CTL_PKE_NONE | PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_DRV_LOW | PAD_CTL_SRE_SLOW), + }, + { + MX53_PIN_DISP0_DAT16, IOMUX_CONFIG_ALT0, + (PAD_CTL_HYS_NONE | PAD_CTL_PKE_NONE | PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_DRV_LOW | PAD_CTL_SRE_SLOW), + }, + { + MX53_PIN_DISP0_DAT17, IOMUX_CONFIG_ALT0, + (PAD_CTL_HYS_NONE | PAD_CTL_PKE_NONE | PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_DRV_LOW | PAD_CTL_SRE_SLOW), + }, + { + MX53_PIN_DISP0_DAT18, IOMUX_CONFIG_ALT0, + (PAD_CTL_HYS_NONE | PAD_CTL_PKE_NONE | PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_DRV_LOW | PAD_CTL_SRE_SLOW), + }, + { + MX53_PIN_DISP0_DAT19, IOMUX_CONFIG_ALT0, + (PAD_CTL_HYS_NONE | PAD_CTL_PKE_NONE | PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_DRV_LOW | PAD_CTL_SRE_SLOW), + }, + { + MX53_PIN_DISP0_DAT20, IOMUX_CONFIG_ALT0, + (PAD_CTL_HYS_NONE | PAD_CTL_PKE_NONE | PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_DRV_LOW | PAD_CTL_SRE_SLOW), + }, + { + MX53_PIN_DISP0_DAT21, IOMUX_CONFIG_ALT0, + (PAD_CTL_HYS_NONE | PAD_CTL_PKE_NONE | PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_DRV_LOW | PAD_CTL_SRE_SLOW), + }, + { + MX53_PIN_DISP0_DAT22, IOMUX_CONFIG_ALT0, + (PAD_CTL_HYS_NONE | PAD_CTL_PKE_NONE | PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_DRV_LOW | PAD_CTL_SRE_SLOW), + }, + { + MX53_PIN_DISP0_DAT23, IOMUX_CONFIG_ALT0, + (PAD_CTL_HYS_NONE | PAD_CTL_PKE_NONE | PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_DRV_LOW | PAD_CTL_SRE_SLOW), + }, + { /* gpio backlight */ + MX53_PIN_DI0_PIN4, IOMUX_CONFIG_ALT1, + (PAD_CTL_HYS_NONE | PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | + PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_SLOW), + }, + /* esdhc1 */ + { + MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION, + (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST), + }, + { + MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION, + (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST), + }, + { + MX53_PIN_SD1_DATA0, IOMUX_CONFIG_ALT0, + (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST), + }, + { + MX53_PIN_SD1_DATA1, IOMUX_CONFIG_ALT0, + (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST), + }, + { + MX53_PIN_SD1_DATA2, IOMUX_CONFIG_ALT0, + (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST), + }, + { + MX53_PIN_SD1_DATA3, IOMUX_CONFIG_ALT0, + (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST), + }, + /* esdhc3 */ + { + MX53_PIN_ATA_DATA0, IOMUX_CONFIG_ALT4, + (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST), + }, + { + MX53_PIN_ATA_DATA1, IOMUX_CONFIG_ALT4, + (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST), + }, + { + MX53_PIN_ATA_DATA2, IOMUX_CONFIG_ALT4, + (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST), + }, + { + MX53_PIN_ATA_DATA3, IOMUX_CONFIG_ALT4, + (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST), + }, + { + MX53_PIN_ATA_DATA8, IOMUX_CONFIG_ALT4, + (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST), + }, + { + MX53_PIN_ATA_DATA9, IOMUX_CONFIG_ALT4, + (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST), + }, + { + MX53_PIN_ATA_DATA10, IOMUX_CONFIG_ALT4, + (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST), + }, + { + MX53_PIN_ATA_DATA11, IOMUX_CONFIG_ALT4, + (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST), + }, + { + MX53_PIN_ATA_IORDY, IOMUX_CONFIG_ALT2, + (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST), + }, + { + MX53_PIN_ATA_RESET_B, IOMUX_CONFIG_ALT2, + (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST), + }, + { /* FEC pins */ + MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0, + PAD_CTL_SRE_FAST, + MUX_IN_FEC_FEC_MDI_SELECT_INPUT, + INPUT_CTL_PATH1, + }, + { + MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT0, + (PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL), + }, + { + MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT0, + (PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL), + }, + { + MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT0, + (PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL), + }, + { + MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT0, + (PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL), + }, + { + MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT0, + (PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL), + }, + { + MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT0, + PAD_CTL_DRV_HIGH, + }, + { + MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT0, + PAD_CTL_DRV_HIGH, + }, + { + MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT0, + PAD_CTL_DRV_HIGH, + }, + { + MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0, + PAD_CTL_DRV_HIGH, + }, + { + MX53_PIN_ATA_DA_0, IOMUX_CONFIG_ALT1, + }, + { /* audio clock out */ + MX53_PIN_GPIO_0, IOMUX_CONFIG_ALT3, + }, +}; + +static int __initdata enable_w1 = { 0 }; +static int __init w1_setup(char *__unused) +{ + enable_w1 = 1; + return 1; +} + +__setup("w1", w1_setup); + +void __init mx53_evk_io_init(void) +{ + int i; + + /* Host1 Vbus with GPIO high */ + mxc_iomux_set_pad(MX53_PIN_ATA_DA_2, PAD_CTL_DRV_HIGH | + PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); + gpio_request(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_2), "gpio7_8"); + gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_2), 1); + + /* USB HUB RESET - De-assert USB HUB RESET_N */ + mxc_iomux_set_pad(MX53_PIN_CSI0_DATA_EN, PAD_CTL_DRV_HIGH | + PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); + gpio_request(IOMUX_TO_GPIO(MX53_PIN_CSI0_DATA_EN), "gpio5_20"); + gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_CSI0_DATA_EN), 0); + + msleep(1); + gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_CSI0_DATA_EN), 0); + msleep(1); + gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_CSI0_DATA_EN), 1); + + /* Enable OTG VBus with GPIO low */ + mxc_iomux_set_pad(MX53_PIN_EIM_A23, PAD_CTL_DRV_HIGH | + PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); + gpio_request(IOMUX_TO_GPIO(MX53_PIN_EIM_A23), "gpio6_6"); + gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_EIM_A23), 0); + gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_EIM_A23), 0); + + for (i = 0; i < ARRAY_SIZE(mxc_iomux_pins); i++) { + mxc_request_iomux(mxc_iomux_pins[i].pin, + mxc_iomux_pins[i].mux_mode); + if (mxc_iomux_pins[i].pad_cfg) + mxc_iomux_set_pad(mxc_iomux_pins[i].pin, + mxc_iomux_pins[i].pad_cfg); + if (mxc_iomux_pins[i].in_select) + mxc_iomux_set_input(mxc_iomux_pins[i].in_select, + mxc_iomux_pins[i].in_mode); + } + + gpio_request(IOMUX_TO_GPIO(MX53_PIN_GPIO_1), "gpio1_1"); + gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_GPIO_1), 0); + gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_1), 1); /*BL*/ + + gpio_request(IOMUX_TO_GPIO(MX53_PIN_GPIO_16), "gpio7_11"); + gpio_direction_input(IOMUX_TO_GPIO(MX53_PIN_GPIO_16)); /*PMIC_INT*/ + + gpio_request(IOMUX_TO_GPIO(MX53_PIN_EIM_DA13), "gpio3_13"); + gpio_direction_input(IOMUX_TO_GPIO(MX53_PIN_EIM_DA13)); /* SD1 CD */ + gpio_request(IOMUX_TO_GPIO(MX53_PIN_EIM_DA14), "gpio3_14"); + gpio_direction_input(IOMUX_TO_GPIO(MX53_PIN_EIM_DA14)); /* SD1 WP */ + + /* SD3 CD */ + gpio_request(IOMUX_TO_GPIO(MX53_PIN_EIM_DA11), "gpio3_11"); + gpio_direction_input(IOMUX_TO_GPIO(MX53_PIN_EIM_DA11)); + + /* SD3 WP */ + gpio_request(IOMUX_TO_GPIO(MX53_PIN_EIM_DA12), "gpio3_12"); + gpio_direction_input(IOMUX_TO_GPIO(MX53_PIN_EIM_DA11)); + + /* reset FEC PHY */ + gpio_request(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_0), "gpio7_6"); + gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_0), 0); + gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_0), 0); + msleep(1); + gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_0), 1); + + + /* i2c1 SDA */ + mxc_request_iomux(MX53_PIN_CSI0_D8, + IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION); + mxc_iomux_set_input(MUX_IN_I2C1_IPP_SDA_IN_SELECT_INPUT, + INPUT_CTL_PATH0); + mxc_iomux_set_pad(MX53_PIN_CSI0_D8, PAD_CTL_SRE_FAST | + PAD_CTL_ODE_OPENDRAIN_ENABLE | + PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | + PAD_CTL_HYS_ENABLE); + + /* i2c1 SCL */ + mxc_request_iomux(MX53_PIN_CSI0_D9, + IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION); + mxc_iomux_set_input(MUX_IN_I2C1_IPP_SCL_IN_SELECT_INPUT, + INPUT_CTL_PATH0); + mxc_iomux_set_pad(MX53_PIN_CSI0_D9, PAD_CTL_SRE_FAST | + PAD_CTL_ODE_OPENDRAIN_ENABLE | + PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | + PAD_CTL_HYS_ENABLE); + + /* i2c2 SDA */ + mxc_request_iomux(MX53_PIN_KEY_ROW3, + IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION); + mxc_iomux_set_input(MUX_IN_I2C2_IPP_SDA_IN_SELECT_INPUT, + INPUT_CTL_PATH0); + mxc_iomux_set_pad(MX53_PIN_KEY_ROW3, + PAD_CTL_SRE_FAST | + PAD_CTL_ODE_OPENDRAIN_ENABLE | + PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | + PAD_CTL_HYS_ENABLE); + + /* i2c2 SCL */ + mxc_request_iomux(MX53_PIN_KEY_COL3, + IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION); + mxc_iomux_set_input(MUX_IN_I2C2_IPP_SCL_IN_SELECT_INPUT, + INPUT_CTL_PATH0); + mxc_iomux_set_pad(MX53_PIN_KEY_COL3, + PAD_CTL_SRE_FAST | + PAD_CTL_ODE_OPENDRAIN_ENABLE | + PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | + PAD_CTL_HYS_ENABLE); + + /* headphone_det_b */ + mxc_request_iomux(MX53_PIN_ATA_DATA5, IOMUX_CONFIG_GPIO); + mxc_iomux_set_pad(MX53_PIN_ATA_DATA5, PAD_CTL_100K_PU); + gpio_request(IOMUX_TO_GPIO(MX53_PIN_ATA_DATA5), "gpio2_5"); + gpio_direction_input(IOMUX_TO_GPIO(MX53_PIN_ATA_DATA5)); + + /* power key */ + + /* LCD related gpio */ + + /* Camera reset */ + + /* Camera low power */ + +} + +/* workaround for ecspi chipselect pin may not keep correct level when idle */ +void mx53_evk_gpio_spi_chipselect_active(int cspi_mode, int status, + int chipselect) +{ + u32 gpio; + + switch (cspi_mode) { + case 1: + switch (chipselect) { + case 0x1: + mxc_request_iomux(MX53_PIN_EIM_D19, + IOMUX_CONFIG_ALT4); + mxc_iomux_set_pad(MX53_PIN_EIM_D19, + PAD_CTL_HYS_ENABLE | + PAD_CTL_PKE_ENABLE | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + break; + case 0x2: + gpio = IOMUX_TO_GPIO(MX53_PIN_EIM_D19); + mxc_request_iomux(MX53_PIN_EIM_D19, + IOMUX_CONFIG_GPIO); + gpio_request(gpio, "cspi1_ss1"); + gpio_direction_output(gpio, 0); + gpio_set_value(gpio, 1 & (~status)); + break; + default: + break; + } + break; + case 2: + break; + case 3: + break; + default: + break; + } +} +EXPORT_SYMBOL(mx53_evk_gpio_spi_chipselect_active); + +void mx53_evk_gpio_spi_chipselect_inactive(int cspi_mode, int status, + int chipselect) +{ + switch (cspi_mode) { + case 1: + switch (chipselect) { + case 0x1: + mxc_free_iomux(MX53_PIN_EIM_D19, IOMUX_CONFIG_ALT4); + mxc_request_iomux(MX53_PIN_EIM_D19, + IOMUX_CONFIG_GPIO); + mxc_free_iomux(MX53_PIN_EIM_D19, IOMUX_CONFIG_GPIO); + break; + case 0x2: + mxc_free_iomux(MX53_PIN_EIM_D19, IOMUX_CONFIG_GPIO); + break; + default: + break; + } + break; + case 2: + break; + case 3: + break; + default: + break; + } +} +EXPORT_SYMBOL(mx53_evk_gpio_spi_chipselect_inactive); + +void gpio_lcd_active(void) +{ +/* TO DO */ +} +EXPORT_SYMBOL(gpio_lcd_active); diff --git a/arch/arm/mach-mx5/mx53_evk_pmic_mc13892.c b/arch/arm/mach-mx5/mx53_evk_pmic_mc13892.c new file mode 100644 index 000000000000..805b3e58cc9d --- /dev/null +++ b/arch/arm/mach-mx5/mx53_evk_pmic_mc13892.c @@ -0,0 +1,353 @@ +/* + * mx53-evk-pmic-mc13892.c -- i.MX53 3STACK Driver for Atlas MC13892 PMIC + */ + /* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + */ + + /* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include <linux/module.h> +#include <linux/init.h> +#include <linux/platform_device.h> +#include <linux/i2c.h> +#include <linux/err.h> +#include <linux/pmic_external.h> +#include <linux/regulator/machine.h> +#include <linux/mfd/mc13892/core.h> +#include <mach/irqs.h> +#include "iomux.h" +#include "mx53_pins.h" + +/* + * Convenience conversion. + * Here atm, maybe there is somewhere better for this. + */ +#define mV_to_uV(mV) (mV * 1000) +#define uV_to_mV(uV) (uV / 1000) +#define V_to_uV(V) (mV_to_uV(V * 1000)) +#define uV_to_V(uV) (uV_to_mV(uV) / 1000) + +#define STANDBYSECINV_LSH 11 +#define STANDBYSECINV_WID 1 + +/* Coin cell charger enable */ +#define CIONCHEN_LSH 23 +#define CIONCHEN_WID 1 +/* Coin cell charger voltage setting */ +#define VCOIN_LSH 20 +#define VCOIN_WID 3 + +/* Coin Charger voltage */ +#define VCOIN_2_5V 0x0 +#define VCOIN_2_7V 0x1 +#define VCOIN_2_8V 0x2 +#define VCOIN_2_9V 0x3 +#define VCOIN_3_0V 0x4 +#define VCOIN_3_1V 0x5 +#define VCOIN_3_2V 0x6 +#define VCOIN_3_3V 0x7 + +/* Keeps VSRTC and CLK32KMCU on for all states */ +#define DRM_LSH 4 +#define DRM_WID 1 + +/* CPU */ +static struct regulator_consumer_supply sw1_consumers[] = { + { + .supply = "cpu_vcc", + } +}; + +struct mc13892; + +static struct regulator_init_data sw1_init = { + .constraints = { + .name = "SW1", + .min_uV = mV_to_uV(600), + .max_uV = mV_to_uV(1375), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .valid_modes_mask = 0, + .always_on = 1, + .boot_on = 1, + .initial_state = PM_SUSPEND_MEM, + .state_mem = { + .uV = 850000, + .mode = REGULATOR_MODE_NORMAL, + .enabled = 1, + }, + }, + .num_consumer_supplies = ARRAY_SIZE(sw1_consumers), + .consumer_supplies = sw1_consumers, +}; + +static struct regulator_init_data sw2_init = { + .constraints = { + .name = "SW2", + .min_uV = mV_to_uV(900), + .max_uV = mV_to_uV(1850), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .always_on = 1, + .boot_on = 1, + .initial_state = PM_SUSPEND_MEM, + .state_mem = { + .uV = 950000, + .mode = REGULATOR_MODE_NORMAL, + .enabled = 1, + }, + } +}; + +static struct regulator_init_data sw3_init = { + .constraints = { + .name = "SW3", + .min_uV = mV_to_uV(1100), + .max_uV = mV_to_uV(1850), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .always_on = 1, + .boot_on = 1, + } +}; + +static struct regulator_init_data sw4_init = { + .constraints = { + .name = "SW4", + .min_uV = mV_to_uV(1100), + .max_uV = mV_to_uV(1850), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .always_on = 1, + .boot_on = 1, + } +}; + +static struct regulator_init_data viohi_init = { + .constraints = { + .name = "VIOHI", + .boot_on = 1, + } +}; + +static struct regulator_init_data vusb_init = { + .constraints = { + .name = "VUSB", + .boot_on = 1, + } +}; + +static struct regulator_init_data swbst_init = { + .constraints = { + .name = "SWBST", + } +}; + +static struct regulator_init_data vdig_init = { + .constraints = { + .name = "VDIG", + .min_uV = mV_to_uV(1050), + .max_uV = mV_to_uV(1800), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .boot_on = 1, + } +}; + +static struct regulator_init_data vpll_init = { + .constraints = { + .name = "VPLL", + .min_uV = mV_to_uV(1050), + .max_uV = mV_to_uV(1800), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .boot_on = 1, + } +}; + +static struct regulator_init_data vusb2_init = { + .constraints = { + .name = "VUSB2", + .min_uV = mV_to_uV(2400), + .max_uV = mV_to_uV(2775), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .boot_on = 1, + } +}; + +static struct regulator_init_data vvideo_init = { + .constraints = { + .name = "VVIDEO", + .min_uV = mV_to_uV(2500), + .max_uV = mV_to_uV(2775), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + } +}; + +static struct regulator_init_data vaudio_init = { + .constraints = { + .name = "VAUDIO", + .min_uV = mV_to_uV(2300), + .max_uV = mV_to_uV(3000), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + } +}; + +static struct regulator_init_data vsd_init = { + .constraints = { + .name = "VSD", + .min_uV = mV_to_uV(1800), + .max_uV = mV_to_uV(3150), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + } +}; + +static struct regulator_init_data vcam_init = { + .constraints = { + .name = "VCAM", + .min_uV = mV_to_uV(2500), + .max_uV = mV_to_uV(3000), + .valid_ops_mask = + REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE, + .valid_modes_mask = REGULATOR_MODE_FAST | REGULATOR_MODE_NORMAL, + } +}; + +static struct regulator_init_data vgen1_init = { + .constraints = { + .name = "VGEN1", + .min_uV = mV_to_uV(1200), + .max_uV = mV_to_uV(3150), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + } +}; + +static struct regulator_init_data vgen2_init = { + .constraints = { + .name = "VGEN2", + .min_uV = mV_to_uV(1200), + .max_uV = mV_to_uV(3150), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .boot_on = 1, + } +}; + +static struct regulator_init_data vgen3_init = { + .constraints = { + .name = "VGEN3", + .min_uV = mV_to_uV(1800), + .max_uV = mV_to_uV(2900), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + } +}; + +static struct regulator_init_data gpo1_init = { + .constraints = { + .name = "GPO1", + } +}; + +static struct regulator_init_data gpo2_init = { + .constraints = { + .name = "GPO2", + } +}; + +static struct regulator_init_data gpo3_init = { + .constraints = { + .name = "GPO3", + } +}; + +static struct regulator_init_data gpo4_init = { + .constraints = { + .name = "GPO4", + } +}; + +/*! + * the event handler for power on event + */ +static void power_on_evt_handler(void) +{ + pr_info("pwr on event1 is received \n"); +} + +static int mc13892_regulator_init(struct mc13892 *mc13892) +{ + unsigned int value; + pmic_event_callback_t power_key_event; + int register_mask; + + printk("Initializing regulators for 3-stack.\n"); + if (mxc_cpu_is_rev(CHIP_REV_2_0) < 0) + sw2_init.constraints.state_mem.uV = 1100000; + else if (mxc_cpu_is_rev(CHIP_REV_2_0) == 1) { + sw2_init.constraints.state_mem.uV = 1250000; + sw1_init.constraints.state_mem.uV = 1000000; + } + + /* subscribe PWRON1 event to enable ON_OFF key */ + power_key_event.param = NULL; + power_key_event.func = (void *)power_on_evt_handler; + pmic_event_subscribe(EVENT_PWRONI, power_key_event); + + /* Bit 4 DRM: keep VSRTC and CLK32KMCU on for all states */ +#if defined(CONFIG_RTC_DRV_MXC_V2) || defined(CONFIG_RTC_DRV_MXC_V2_MODULE) + value = BITFVAL(DRM, 1); + register_mask = BITFMASK(DRM); + pmic_write_reg(REG_POWER_CTL0, value, register_mask); +#endif + /* Set the STANDBYSECINV bit, so that STANDBY pin is + * interpreted as active low. + */ + value = BITFVAL(STANDBYSECINV, 1); + register_mask = BITFMASK(STANDBYSECINV); + pmic_write_reg(REG_POWER_CTL2, value, register_mask); + + /* Enable coin cell charger */ + value = BITFVAL(CIONCHEN, 1) | BITFVAL(VCOIN, VCOIN_3_0V); + register_mask = BITFMASK(CIONCHEN) | BITFMASK(VCOIN); + pmic_write_reg(REG_POWER_CTL0, value, register_mask); + + mc13892_register_regulator(mc13892, MC13892_SW1, &sw1_init); + mc13892_register_regulator(mc13892, MC13892_SW2, &sw2_init); + mc13892_register_regulator(mc13892, MC13892_SW3, &sw3_init); + mc13892_register_regulator(mc13892, MC13892_SW4, &sw4_init); + mc13892_register_regulator(mc13892, MC13892_SWBST, &swbst_init); + mc13892_register_regulator(mc13892, MC13892_VIOHI, &viohi_init); + mc13892_register_regulator(mc13892, MC13892_VPLL, &vpll_init); + mc13892_register_regulator(mc13892, MC13892_VDIG, &vdig_init); + mc13892_register_regulator(mc13892, MC13892_VSD, &vsd_init); + mc13892_register_regulator(mc13892, MC13892_VUSB2, &vusb2_init); + mc13892_register_regulator(mc13892, MC13892_VVIDEO, &vvideo_init); + mc13892_register_regulator(mc13892, MC13892_VAUDIO, &vaudio_init); + mc13892_register_regulator(mc13892, MC13892_VCAM, &vcam_init); + mc13892_register_regulator(mc13892, MC13892_VGEN1, &vgen1_init); + mc13892_register_regulator(mc13892, MC13892_VGEN2, &vgen2_init); + mc13892_register_regulator(mc13892, MC13892_VGEN3, &vgen3_init); + mc13892_register_regulator(mc13892, MC13892_VUSB, &vusb_init); + mc13892_register_regulator(mc13892, MC13892_GPO1, &gpo1_init); + mc13892_register_regulator(mc13892, MC13892_GPO2, &gpo2_init); + mc13892_register_regulator(mc13892, MC13892_GPO3, &gpo3_init); + mc13892_register_regulator(mc13892, MC13892_GPO4, &gpo4_init); + + return 0; +} + +static struct mc13892_platform_data mc13892_plat = { + .init = mc13892_regulator_init, +}; + +static struct i2c_board_info __initdata mc13892_i2c_device = { + I2C_BOARD_INFO("mc13892", 0x08), + .irq = IOMUX_TO_IRQ(MX53_PIN_GPIO_16), + .platform_data = &mc13892_plat, +}; + +int __init mx53_evk_init_mc13892(void) +{ + return i2c_register_board_info(1, &mc13892_i2c_device, 1); +} diff --git a/arch/arm/mach-mx5/mx53_pins.h b/arch/arm/mach-mx5/mx53_pins.h new file mode 100644 index 000000000000..bf83e9870538 --- /dev/null +++ b/arch/arm/mach-mx5/mx53_pins.h @@ -0,0 +1,421 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ +#ifndef __ASM_ARCH_MXC_MX53_PINS_H__ +#define __ASM_ARCH_MXC_MX53_PINS_H__ +#include "iomux.h" + +/*! + * @file arch-mxc/mx53_pins.h + * + * @brief MX53 I/O Pin List + * + * @ingroup GPIO_MX53 + */ + +#ifndef __ASSEMBLY__ + +#define PAD_I_START_MX53 0x348 + +#define _MXC_BUILD_PIN_MX53(gp, gi, ga, mi, pi) \ + (((gp) << MUX_IO_P) | ((gi) << MUX_IO_I) | \ + ((mi) << MUX_I) | \ + ((pi - PAD_I_START_MX53) << PAD_I) | \ + ((ga) << GPIO_I)) + +#define _MXC_BUILD_GPIO_PIN_MX53(gp, gi, ga, mi, pi) \ + _MXC_BUILD_PIN_MX53(gp, gi, ga, mi, pi) + +#define _MXC_BUILD_NON_GPIO_PIN_MX53(mi, pi) \ + _MXC_BUILD_PIN_MX53(NON_GPIO_PORT, 0, 0, mi, pi) +/*! + * This enumeration is constructed based on the Section + * "sw_pad_ctl & sw_mux_ctl details" of the MX53 IC Spec. Each enumerated + * value is constructed based on the rules described above. + */ +enum iomux_pins { + MX53_PIN_GPIO_19 = _MXC_BUILD_GPIO_PIN_MX53(3, 5, 1, 0x20, 0x348), + MX53_PIN_KEY_COL0 = _MXC_BUILD_GPIO_PIN_MX53(3, 6, 1, 0x24, 0x34C), + MX53_PIN_KEY_ROW0 = _MXC_BUILD_GPIO_PIN_MX53(3, 7, 1, 0x28, 0x350), + MX53_PIN_KEY_COL1 = _MXC_BUILD_GPIO_PIN_MX53(3, 8, 1, 0x2C, 0x354), + MX53_PIN_KEY_ROW1 = _MXC_BUILD_GPIO_PIN_MX53(3, 9, 1, 0x30, 0x358), + MX53_PIN_KEY_COL2 = _MXC_BUILD_GPIO_PIN_MX53(3, 10, 1, 0x34, 0x35C), + MX53_PIN_KEY_ROW2 = _MXC_BUILD_GPIO_PIN_MX53(3, 11, 1, 0x38, 0x360), + MX53_PIN_KEY_COL3 = _MXC_BUILD_GPIO_PIN_MX53(3, 12, 1, 0x3C, 0x364), + MX53_PIN_KEY_ROW3 = _MXC_BUILD_GPIO_PIN_MX53(3, 13, 1, 0x40, 0x368), + MX53_PIN_KEY_COL4 = _MXC_BUILD_GPIO_PIN_MX53(3, 14, 1, 0x44, 0x36C), + MX53_PIN_KEY_ROW4 = _MXC_BUILD_GPIO_PIN_MX53(3, 15, 1, 0x48, 0x370), + MX53_PIN_NVCC_KEYPAD = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x374), + MX53_PIN_DI0_DISP_CLK = _MXC_BUILD_GPIO_PIN_MX53(3, 16, 1, 0x4C, 0x378), + MX53_PIN_DI0_PIN15 = _MXC_BUILD_GPIO_PIN_MX53(3, 17, 1, 0x50, 0x37C), + MX53_PIN_DI0_PIN2 = _MXC_BUILD_GPIO_PIN_MX53(3, 18, 1, 0x54, 0x380), + MX53_PIN_DI0_PIN3 = _MXC_BUILD_GPIO_PIN_MX53(3, 19, 1, 0x58, 0x384), + MX53_PIN_DI0_PIN4 = _MXC_BUILD_GPIO_PIN_MX53(3, 20, 1, 0x5C, 0x388), + MX53_PIN_DISP0_DAT0 = _MXC_BUILD_GPIO_PIN_MX53(3, 21, 1, 0x60, 0x38C), + MX53_PIN_DISP0_DAT1 = _MXC_BUILD_GPIO_PIN_MX53(3, 22, 1, 0x64, 0x390), + MX53_PIN_DISP0_DAT2 = _MXC_BUILD_GPIO_PIN_MX53(3, 23, 1, 0x68, 0x394), + MX53_PIN_DISP0_DAT3 = _MXC_BUILD_GPIO_PIN_MX53(3, 24, 1, 0x6C, 0x398), + MX53_PIN_DISP0_DAT4 = _MXC_BUILD_GPIO_PIN_MX53(3, 25, 1, 0x70, 0x39C), + MX53_PIN_DISP0_DAT5 = _MXC_BUILD_GPIO_PIN_MX53(3, 26, 1, 0x74, 0x3A0), + MX53_PIN_DISP0_DAT6 = _MXC_BUILD_GPIO_PIN_MX53(3, 27, 1, 0x78, 0x3A4), + MX53_PIN_DISP0_DAT7 = _MXC_BUILD_GPIO_PIN_MX53(3, 28, 1, 0x7C, 0x3A8), + MX53_PIN_DISP0_DAT8 = _MXC_BUILD_GPIO_PIN_MX53(3, 29, 1, 0x80, 0x3AC), + MX53_PIN_DISP0_DAT9 = _MXC_BUILD_GPIO_PIN_MX53(3, 30, 1, 0x84, 0x3B0), + MX53_PIN_DISP0_DAT10 = _MXC_BUILD_GPIO_PIN_MX53(3, 31, 1, 0x88, 0x3B4), + MX53_PIN_DISP0_DAT11 = _MXC_BUILD_GPIO_PIN_MX53(4, 5, 1, 0x8C, 0x3B8), + MX53_PIN_DISP0_DAT12 = _MXC_BUILD_GPIO_PIN_MX53(4, 6, 1, 0x90, 0x3BC), + MX53_PIN_DISP0_DAT13 = _MXC_BUILD_GPIO_PIN_MX53(4, 7, 1, 0x94, 0x3C0), + MX53_PIN_DISP0_DAT14 = _MXC_BUILD_GPIO_PIN_MX53(4, 8, 1, 0x98, 0x3C4), + MX53_PIN_DISP0_DAT15 = _MXC_BUILD_GPIO_PIN_MX53(4, 9, 1, 0x9C, 0x3C8), + MX53_PIN_DISP0_DAT16 = _MXC_BUILD_GPIO_PIN_MX53(4, 10, 1, 0xA0, 0x3CC), + MX53_PIN_DISP0_DAT17 = _MXC_BUILD_GPIO_PIN_MX53(4, 11, 1, 0xA4, 0x3D0), + MX53_PIN_DISP0_DAT18 = _MXC_BUILD_GPIO_PIN_MX53(4, 12, 1, 0xA8, 0x3D4), + MX53_PIN_DISP0_DAT19 = _MXC_BUILD_GPIO_PIN_MX53(4, 13, 1, 0xAC, 0x3D8), + MX53_PIN_DISP0_DAT20 = _MXC_BUILD_GPIO_PIN_MX53(4, 14, 1, 0xB0, 0x3DC), + MX53_PIN_DISP0_DAT21 = _MXC_BUILD_GPIO_PIN_MX53(4, 15, 1, 0xB4, 0x3E0), + MX53_PIN_DISP0_DAT22 = _MXC_BUILD_GPIO_PIN_MX53(4, 16, 1, 0xB8, 0x3E4), + MX53_PIN_DISP0_DAT23 = _MXC_BUILD_GPIO_PIN_MX53(4, 17, 1, 0xBC, 0x3E8), + MX53_PIN_CSI0_PIXCLK = _MXC_BUILD_GPIO_PIN_MX53(4, 18, 1, 0xC0, 0x3EC), + MX53_PIN_CSI0_MCLK = _MXC_BUILD_GPIO_PIN_MX53(4, 19, 1, 0xC4, 0x3F0), + MX53_PIN_CSI0_DATA_EN = _MXC_BUILD_GPIO_PIN_MX53(4, 20, 1, 0xC8, 0x3F4), + MX53_PIN_CSI0_VSYNC = _MXC_BUILD_GPIO_PIN_MX53(4, 21, 1, 0xCC, 0x3F8), + MX53_PIN_CSI0_D4 = _MXC_BUILD_GPIO_PIN_MX53(4, 22, 1, 0xD0, 0x3FC), + MX53_PIN_CSI0_D5 = _MXC_BUILD_GPIO_PIN_MX53(4, 23, 1, 0xD4, 0x400), + MX53_PIN_CSI0_D6 = _MXC_BUILD_GPIO_PIN_MX53(4, 24, 1, 0xD8, 0x404), + MX53_PIN_CSI0_D7 = _MXC_BUILD_GPIO_PIN_MX53(4, 25, 1, 0xDC, 0x408), + MX53_PIN_CSI0_D8 = _MXC_BUILD_GPIO_PIN_MX53(4, 26, 1, 0xE0, 0x40C), + MX53_PIN_CSI0_D9 = _MXC_BUILD_GPIO_PIN_MX53(4, 27, 1, 0xE4, 0x410), + MX53_PIN_CSI0_D10 = _MXC_BUILD_GPIO_PIN_MX53(4, 28, 1, 0xE8, 0x414), + MX53_PIN_CSI0_D11 = _MXC_BUILD_GPIO_PIN_MX53(4, 29, 1, 0xEC, 0x418), + MX53_PIN_CSI0_D12 = _MXC_BUILD_GPIO_PIN_MX53(4, 30, 1, 0xF0, 0x41C), + MX53_PIN_CSI0_D13 = _MXC_BUILD_GPIO_PIN_MX53(4, 31, 1, 0xF4, 0x420), + MX53_PIN_CSI0_D14 = _MXC_BUILD_GPIO_PIN_MX53(5, 0, 1, 0xF8, 0x424), + MX53_PIN_CSI0_D15 = _MXC_BUILD_GPIO_PIN_MX53(5, 1, 1, 0xFC, 0x428), + MX53_PIN_CSI0_D16 = _MXC_BUILD_GPIO_PIN_MX53(5, 2, 1, 0x100, 0x42C), + MX53_PIN_CSI0_D17 = _MXC_BUILD_GPIO_PIN_MX53(5, 3, 1, 0x104, 0x430), + MX53_PIN_CSI0_D18 = _MXC_BUILD_GPIO_PIN_MX53(5, 4, 1, 0x108, 0x434), + MX53_PIN_CSI0_D19 = _MXC_BUILD_GPIO_PIN_MX53(5, 5, 1, 0x10C, 0x438), + MX53_PIN_NVCC_CSI0 = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x43C), + MX53_PIN_JTAG_TMS = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x440), + MX53_PIN_JTAG_MOD = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x444), + MX53_PIN_JTAG_TRSTB = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x448), + MX53_PIN_JTAG_TDI = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x44C), + MX53_PIN_JTAG_TCK = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x450), + MX53_PIN_JTAG_TDO = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x454), + MX53_PIN_EIM_A25 = _MXC_BUILD_GPIO_PIN_MX53(4, 2, 1, 0x110, 0x458), + MX53_PIN_EIM_EB2 = _MXC_BUILD_GPIO_PIN_MX53(1, 30, 1, 0x114, 0x45C), + MX53_PIN_EIM_D16 = _MXC_BUILD_GPIO_PIN_MX53(2, 16, 1, 0x118, 0x460), + MX53_PIN_EIM_D17 = _MXC_BUILD_GPIO_PIN_MX53(2, 17, 1, 0x11C, 0x464), + MX53_PIN_EIM_D18 = _MXC_BUILD_GPIO_PIN_MX53(2, 18, 1, 0x120, 0x468), + MX53_PIN_EIM_D19 = _MXC_BUILD_GPIO_PIN_MX53(2, 19, 1, 0x124, 0x46C), + MX53_PIN_EIM_D20 = _MXC_BUILD_GPIO_PIN_MX53(2, 20, 1, 0x128, 0x470), + MX53_PIN_EIM_D21 = _MXC_BUILD_GPIO_PIN_MX53(2, 21, 1, 0x12C, 0x474), + MX53_PIN_EIM_D22 = _MXC_BUILD_GPIO_PIN_MX53(2, 22, 1, 0x130, 0x478), + MX53_PIN_EIM_D23 = _MXC_BUILD_GPIO_PIN_MX53(2, 23, 1, 0x134, 0x47C), + MX53_PIN_EIM_EB3 = _MXC_BUILD_GPIO_PIN_MX53(1, 31, 1, 0x138, 0x480), + MX53_PIN_EIM_D24 = _MXC_BUILD_GPIO_PIN_MX53(2, 24, 1, 0x13C, 0x484), + MX53_PIN_EIM_D25 = _MXC_BUILD_GPIO_PIN_MX53(2, 25, 1, 0x140, 0x488), + MX53_PIN_EIM_D26 = _MXC_BUILD_GPIO_PIN_MX53(2, 26, 1, 0x144, 0x48C), + MX53_PIN_EIM_D27 = _MXC_BUILD_GPIO_PIN_MX53(2, 27, 1, 0x148, 0x490), + MX53_PIN_EIM_D28 = _MXC_BUILD_GPIO_PIN_MX53(2, 28, 1, 0x14C, 0x494), + MX53_PIN_EIM_D29 = _MXC_BUILD_GPIO_PIN_MX53(2, 29, 1, 0x150, 0x498), + MX53_PIN_EIM_D30 = _MXC_BUILD_GPIO_PIN_MX53(2, 30, 1, 0x154, 0x49C), + MX53_PIN_EIM_D31 = _MXC_BUILD_GPIO_PIN_MX53(2, 31, 1, 0x158, 0x4A0), + MX53_PIN_NVCC_EIM1 = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x4A4), + MX53_PIN_EIM_A24 = _MXC_BUILD_GPIO_PIN_MX53(4, 4, 1, 0x15C, 0x4A8), + MX53_PIN_EIM_A23 = _MXC_BUILD_GPIO_PIN_MX53(5, 6, 1, 0x160, 0x4AC), + MX53_PIN_EIM_A22 = _MXC_BUILD_GPIO_PIN_MX53(1, 16, 1, 0x164, 0x4B0), + MX53_PIN_EIM_A21 = _MXC_BUILD_GPIO_PIN_MX53(1, 17, 1, 0x168, 0x4B4), + MX53_PIN_EIM_A20 = _MXC_BUILD_GPIO_PIN_MX53(1, 18, 1, 0x16C, 0x4B8), + MX53_PIN_EIM_A19 = _MXC_BUILD_GPIO_PIN_MX53(1, 19, 1, 0x170, 0x4BC), + MX53_PIN_EIM_A18 = _MXC_BUILD_GPIO_PIN_MX53(1, 20, 1, 0x174, 0x4C0), + MX53_PIN_EIM_A17 = _MXC_BUILD_GPIO_PIN_MX53(1, 21, 1, 0x178, 0x4C4), + MX53_PIN_EIM_A16 = _MXC_BUILD_GPIO_PIN_MX53(1, 22, 1, 0x17C, 0x4C8), + MX53_PIN_EIM_CS0 = _MXC_BUILD_GPIO_PIN_MX53(1, 23, 1, 0x180, 0x4CC), + MX53_PIN_EIM_CS1 = _MXC_BUILD_GPIO_PIN_MX53(1, 24, 1, 0x184, 0x4D0), + MX53_PIN_EIM_OE = _MXC_BUILD_GPIO_PIN_MX53(1, 25, 1, 0x188, 0x4D4), + MX53_PIN_EIM_RW = _MXC_BUILD_GPIO_PIN_MX53(1, 26, 1, 0x18C, 0x4D8), + MX53_PIN_EIM_LBA = _MXC_BUILD_GPIO_PIN_MX53(1, 27, 1, 0x190, 0x4DC), + MX53_PIN_NVCC_EIM4 = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x4E0), + MX53_PIN_EIM_EB0 = _MXC_BUILD_GPIO_PIN_MX53(1, 28, 1, 0x194, 0x4E4), + MX53_PIN_EIM_EB1 = _MXC_BUILD_GPIO_PIN_MX53(1, 29, 1, 0x198, 0x4E8), + MX53_PIN_EIM_DA0 = _MXC_BUILD_GPIO_PIN_MX53(2, 0, 1, 0x19C, 0x4EC), + MX53_PIN_EIM_DA1 = _MXC_BUILD_GPIO_PIN_MX53(2, 1, 1, 0x1A0, 0x4F0), + MX53_PIN_EIM_DA2 = _MXC_BUILD_GPIO_PIN_MX53(2, 2, 1, 0x1A4, 0x4F4), + MX53_PIN_EIM_DA3 = _MXC_BUILD_GPIO_PIN_MX53(2, 3, 1, 0x1A8, 0x4F8), + MX53_PIN_EIM_DA4 = _MXC_BUILD_GPIO_PIN_MX53(2, 4, 1, 0x1AC, 0x4FC), + MX53_PIN_EIM_DA5 = _MXC_BUILD_GPIO_PIN_MX53(2, 5, 1, 0x1B0, 0x500), + MX53_PIN_EIM_DA6 = _MXC_BUILD_GPIO_PIN_MX53(2, 6, 1, 0x1B4, 0x504), + MX53_PIN_EIM_DA7 = _MXC_BUILD_GPIO_PIN_MX53(2, 7, 1, 0x1B8, 0x508), + MX53_PIN_EIM_DA8 = _MXC_BUILD_GPIO_PIN_MX53(2, 8, 1, 0x1BC, 0x50C), + MX53_PIN_EIM_DA9 = _MXC_BUILD_GPIO_PIN_MX53(2, 9, 1, 0x1C0, 0x510), + MX53_PIN_EIM_DA10 = _MXC_BUILD_GPIO_PIN_MX53(2, 10, 1, 0x1C4, 0x514), + MX53_PIN_EIM_DA11 = _MXC_BUILD_GPIO_PIN_MX53(2, 11, 1, 0x1C8, 0x518), + MX53_PIN_EIM_DA12 = _MXC_BUILD_GPIO_PIN_MX53(2, 12, 1, 0x1CC, 0x51C), + MX53_PIN_EIM_DA13 = _MXC_BUILD_GPIO_PIN_MX53(2, 13, 1, 0x1D0, 0x520), + MX53_PIN_EIM_DA14 = _MXC_BUILD_GPIO_PIN_MX53(2, 14, 1, 0x1D4, 0x524), + MX53_PIN_EIM_DA15 = _MXC_BUILD_GPIO_PIN_MX53(2, 15, 1, 0x1D8, 0x528), + MX53_PIN_NANDF_WE_B = _MXC_BUILD_GPIO_PIN_MX53(5, 12, 1, 0x1DC, 0x52C), + MX53_PIN_NANDF_RE_B = _MXC_BUILD_GPIO_PIN_MX53(5, 13, 1, 0x1E0, 0x530), + MX53_PIN_EIM_WAIT = _MXC_BUILD_GPIO_PIN_MX53(4, 0, 1, 0x1E4, 0x534), + MX53_PIN_EIM_BCLK = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x538), + MX53_PIN_NVCC_EIM7 = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x53C), + MX53_PIN_LVDS1_TX3_P = _MXC_BUILD_GPIO_PIN_MX53(5, 22, 0, 0x1EC, NON_PAD_I), + MX53_PIN_LVDS1_TX2_P = _MXC_BUILD_GPIO_PIN_MX53(5, 24, 0, 0x1F0, NON_PAD_I), + MX53_PIN_LVDS1_CLK_P = _MXC_BUILD_GPIO_PIN_MX53(5, 26, 0, 0x1F4, NON_PAD_I), + MX53_PIN_LVDS1_TX1_P = _MXC_BUILD_GPIO_PIN_MX53(5, 28, 0, 0x1F8, NON_PAD_I), + MX53_PIN_LVDS1_TX0_P = _MXC_BUILD_GPIO_PIN_MX53(5, 30, 0, 0x1FC, NON_PAD_I), + MX53_PIN_LVDS0_TX3_P = _MXC_BUILD_GPIO_PIN_MX53(6, 22, 0, 0x200, NON_PAD_I), + MX53_PIN_LVDS0_CLK_P = _MXC_BUILD_GPIO_PIN_MX53(6, 24, 0, 0x204, NON_PAD_I), + MX53_PIN_LVDS0_TX2_P = _MXC_BUILD_GPIO_PIN_MX53(6, 26, 0, 0x208, NON_PAD_I), + MX53_PIN_LVDS0_TX1_P = _MXC_BUILD_GPIO_PIN_MX53(6, 28, 0, 0x20C, NON_PAD_I), + MX53_PIN_LVDS0_TX0_P = _MXC_BUILD_GPIO_PIN_MX53(6, 30, 0, 0x210, NON_PAD_I), + MX53_PIN_GPIO_10 = _MXC_BUILD_GPIO_PIN_MX53(3, 0, 0, 0x214, 0x540), + MX53_PIN_GPIO_11 = _MXC_BUILD_GPIO_PIN_MX53(3, 1, 0, 0x218, 0x544), + MX53_PIN_GPIO_12 = _MXC_BUILD_GPIO_PIN_MX53(3, 2, 0, 0x21C, 0x548), + MX53_PIN_GPIO_13 = _MXC_BUILD_GPIO_PIN_MX53(3, 3, 0, 0x220, 0x54C), + MX53_PIN_GPIO_14 = _MXC_BUILD_GPIO_PIN_MX53(3, 4, 0, 0x224, 0x550), + MX53_PIN_DRAM_DQM3 = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x554), + MX53_PIN_DRAM_SDQS3 = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x558), + MX53_PIN_DRAM_SDCKE1 = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x55C), + MX53_PIN_DRAM_DQM2 = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x560), + MX53_PIN_DRAM_SDODT1 = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x564), + MX53_PIN_DRAM_SDQS2 = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x568), + MX53_PIN_DRAM_RESET = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x56C), + MX53_PIN_DRAM_SDCLK1 = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x570), + MX53_PIN_DRAM_CAS = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x574), + MX53_PIN_DRAM_SDCLK0 = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x578), + MX53_PIN_DRAM_SDQS0 = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x57C), + MX53_PIN_DRAM_SDODT0 = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x580), + MX53_PIN_DRAM_DQM0 = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x584), + MX53_PIN_DRAM_RAS = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x588), + MX53_PIN_DRAM_SDCKE0 = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x58C), + MX53_PIN_DRAM_SDQS1 = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x590), + MX53_PIN_DRAM_DQM1 = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x594), + MX53_PIN_PMIC_ON_REQ = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x598), + MX53_PIN_PMIC_STBY_REQ = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x59C), + MX53_PIN_NANDF_CLE = _MXC_BUILD_GPIO_PIN_MX53(5, 7, 1, 0x228, 0x5A0), + MX53_PIN_NANDF_ALE = _MXC_BUILD_GPIO_PIN_MX53(5, 8 , 1, 0x22C, 0x5A4), + MX53_PIN_NANDF_WP_B = _MXC_BUILD_GPIO_PIN_MX53(5, 9, 1, 0x230, 0x5A8), + MX53_PIN_NANDF_RB0 = _MXC_BUILD_GPIO_PIN_MX53(5, 10, 1, 0x234, 0x5AC), + MX53_PIN_NANDF_CS0 = _MXC_BUILD_GPIO_PIN_MX53(5, 11, 1, 0x238, 0x5B0), + MX53_PIN_NANDF_CS1 = _MXC_BUILD_GPIO_PIN_MX53(5, 14, 1, 0x23C, 0x5B4), + MX53_PIN_NANDF_CS2 = _MXC_BUILD_GPIO_PIN_MX53(5, 15, 1, 0x240, 0x5B8), + MX53_PIN_NANDF_CS3 = _MXC_BUILD_GPIO_PIN_MX53(5, 16, 1, 0x244, 0x5BC), + MX53_PIN_NVCC_NANDF = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x5C0), + MX53_PIN_FEC_MDIO = _MXC_BUILD_GPIO_PIN_MX53(0, 22, 1, 0x248, 0x5C4), + MX53_PIN_FEC_REF_CLK = _MXC_BUILD_GPIO_PIN_MX53(0, 23, 1, 0x24C, 0x5C8), + MX53_PIN_FEC_RX_ER = _MXC_BUILD_GPIO_PIN_MX53(0, 24, 1, 0x250, 0x5CC), + MX53_PIN_FEC_CRS_DV = _MXC_BUILD_GPIO_PIN_MX53(0, 25, 1, 0x254, 0x5D0), + MX53_PIN_FEC_RXD1 = _MXC_BUILD_GPIO_PIN_MX53(0, 26, 1, 0x258, 0x5D4), + MX53_PIN_FEC_RXD0 = _MXC_BUILD_GPIO_PIN_MX53(0, 27, 1, 0x25C, 0x5D8), + MX53_PIN_FEC_TX_EN = _MXC_BUILD_GPIO_PIN_MX53(0, 28, 1, 0x260, 0x5DC), + MX53_PIN_FEC_TXD1 = _MXC_BUILD_GPIO_PIN_MX53(0, 29, 1, 0x264, 0x5E0), + MX53_PIN_FEC_TXD0 = _MXC_BUILD_GPIO_PIN_MX53(0, 30, 1, 0x268, 0x5E4), + MX53_PIN_FEC_MDC = _MXC_BUILD_GPIO_PIN_MX53(0, 31, 1, 0x26C, 0x5E8), + MX53_PIN_NVCC_FEC = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x5EC), + MX53_PIN_ATA_DIOW = _MXC_BUILD_GPIO_PIN_MX53(5, 17, 1, 0x270, 0x5F0), + MX53_PIN_ATA_DMACK = _MXC_BUILD_GPIO_PIN_MX53(5, 18, 1, 0x274, 0x5F4), + MX53_PIN_ATA_DMARQ = _MXC_BUILD_GPIO_PIN_MX53(6, 0, 1, 0x278, 0x5F8), + MX53_PIN_ATA_BUFFER_EN = _MXC_BUILD_GPIO_PIN_MX53(6, 1, 1, 0x27C, 0x5FC), + MX53_PIN_ATA_INTRQ = _MXC_BUILD_GPIO_PIN_MX53(6, 2, 1, 0x280, 0x600), + MX53_PIN_ATA_DIOR = _MXC_BUILD_GPIO_PIN_MX53(6, 3, 1, 0x284, 0x604), + MX53_PIN_ATA_RESET_B = _MXC_BUILD_GPIO_PIN_MX53(6, 4, 1, 0x288, 0x608), + MX53_PIN_ATA_IORDY = _MXC_BUILD_GPIO_PIN_MX53(6, 5, 1, 0x28C, 0x60C), + MX53_PIN_ATA_DA_0 = _MXC_BUILD_GPIO_PIN_MX53(6, 6, 1, 0x290, 0x610), + MX53_PIN_ATA_DA_1 = _MXC_BUILD_GPIO_PIN_MX53(6, 7, 1, 0x294, 0x614), + MX53_PIN_ATA_DA_2 = _MXC_BUILD_GPIO_PIN_MX53(6, 8, 1, 0x298, 0x618), + MX53_PIN_ATA_CS_0 = _MXC_BUILD_GPIO_PIN_MX53(6, 9, 1, 0x29C, 0x61C), + MX53_PIN_ATA_CS_1 = _MXC_BUILD_GPIO_PIN_MX53(6, 10, 1, 0x2A0, 0x620), + MX53_PIN_NVCC_ATA2 = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x624), + MX53_PIN_ATA_DATA0 = _MXC_BUILD_GPIO_PIN_MX53(1, 0, 1, 0x2A4, 0x628), + MX53_PIN_ATA_DATA1 = _MXC_BUILD_GPIO_PIN_MX53(1, 1, 1, 0x2A8, 0x62C), + MX53_PIN_ATA_DATA2 = _MXC_BUILD_GPIO_PIN_MX53(1, 2, 1, 0x2AC, 0x630), + MX53_PIN_ATA_DATA3 = _MXC_BUILD_GPIO_PIN_MX53(1, 3, 1, 0x2B0, 0x634), + MX53_PIN_ATA_DATA4 = _MXC_BUILD_GPIO_PIN_MX53(1, 4, 1, 0x2B4, 0x638), + MX53_PIN_ATA_DATA5 = _MXC_BUILD_GPIO_PIN_MX53(1, 5, 1, 0x2B8, 0x63C), + MX53_PIN_ATA_DATA6 = _MXC_BUILD_GPIO_PIN_MX53(1, 6, 1, 0x2BC, 0x640), + MX53_PIN_ATA_DATA7 = _MXC_BUILD_GPIO_PIN_MX53(1, 7, 1, 0x2C0, 0x644), + MX53_PIN_ATA_DATA8 = _MXC_BUILD_GPIO_PIN_MX53(1, 8, 1, 0x2C4, 0x648), + MX53_PIN_ATA_DATA9 = _MXC_BUILD_GPIO_PIN_MX53(1, 9, 1, 0x2C8, 0x64C), + MX53_PIN_ATA_DATA10 = _MXC_BUILD_GPIO_PIN_MX53(1, 10, 1, 0x2CC, 0x650), + MX53_PIN_ATA_DATA11 = _MXC_BUILD_GPIO_PIN_MX53(1, 11, 1, 0x2D0, 0x654), + MX53_PIN_ATA_DATA12 = _MXC_BUILD_GPIO_PIN_MX53(1, 12, 1, 0x2D4, 0x658), + MX53_PIN_ATA_DATA13 = _MXC_BUILD_GPIO_PIN_MX53(1, 13, 1, 0x2D8, 0x65C), + MX53_PIN_ATA_DATA14 = _MXC_BUILD_GPIO_PIN_MX53(1, 14, 1, 0x2DC, 0x660), + MX53_PIN_ATA_DATA15 = _MXC_BUILD_GPIO_PIN_MX53(1, 15, 1, 0x2E0, 0x664), + MX53_PIN_NVCC_ATA0 = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x668), + MX53_PIN_SD1_DATA0 = _MXC_BUILD_GPIO_PIN_MX53(0, 16, 1, 0x2E4, 0x66C), + MX53_PIN_SD1_DATA1 = _MXC_BUILD_GPIO_PIN_MX53(0, 17, 1, 0x2E8, 0x670), + MX53_PIN_SD1_CMD = _MXC_BUILD_GPIO_PIN_MX53(0, 18, 1, 0x2EC, 0x674), + MX53_PIN_SD1_DATA2 = _MXC_BUILD_GPIO_PIN_MX53(0, 19, 1, 0x2F0, 0x678), + MX53_PIN_SD1_CLK = _MXC_BUILD_GPIO_PIN_MX53(0, 20, 1, 0x2F4, 0x67C), + MX53_PIN_SD1_DATA3 = _MXC_BUILD_GPIO_PIN_MX53(0, 21, 1, 0x2F8, 0x680), + MX53_PIN_NVCC_SD1 = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x684), + MX53_PIN_SD2_CLK = _MXC_BUILD_GPIO_PIN_MX53(0, 10, 1, 0x2FC, 0x688), + MX53_PIN_SD2_CMD = _MXC_BUILD_GPIO_PIN_MX53(0, 11, 1, 0x300, 0x68C), + MX53_PIN_SD2_DATA3 = _MXC_BUILD_GPIO_PIN_MX53(0, 12, 1, 0x304, 0x690), + MX53_PIN_SD2_DATA2 = _MXC_BUILD_GPIO_PIN_MX53(0, 13, 1, 0x308, 0x694), + MX53_PIN_SD2_DATA1 = _MXC_BUILD_GPIO_PIN_MX53(0, 14, 1, 0x30C, 0x698), + MX53_PIN_SD2_DATA0 = _MXC_BUILD_GPIO_PIN_MX53(0, 15, 1, 0x310, 0x69C), + MX53_PIN_NVCC_SD2 = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x6A0), + MX53_PIN_GPIO_0 = _MXC_BUILD_GPIO_PIN_MX53(0, 0, 1, 0x314, 0x6A4), + MX53_PIN_GPIO_1 = _MXC_BUILD_GPIO_PIN_MX53(0, 1, 1, 0x318, 0x6A8), + MX53_PIN_GPIO_9 = _MXC_BUILD_GPIO_PIN_MX53(0, 9, 1, 0x31C, 0x6AC), + MX53_PIN_GPIO_3 = _MXC_BUILD_GPIO_PIN_MX53(0, 3, 1, 0x320, 0x6B0), + MX53_PIN_GPIO_6 = _MXC_BUILD_GPIO_PIN_MX53(0, 6, 1, 0x324, 0x6B4), + MX53_PIN_GPIO_2 = _MXC_BUILD_GPIO_PIN_MX53(0, 2, 1, 0x328, 0x6B8), + MX53_PIN_GPIO_4 = _MXC_BUILD_GPIO_PIN_MX53(0, 4, 1, 0x32C, 0x6BC), + MX53_PIN_GPIO_5 = _MXC_BUILD_GPIO_PIN_MX53(0, 5, 1, 0x330, 0x6C0), + MX53_PIN_GPIO_7 = _MXC_BUILD_GPIO_PIN_MX53(0, 7, 1, 0x334, 0x6C4), + MX53_PIN_GPIO_8 = _MXC_BUILD_GPIO_PIN_MX53(0, 8, 1, 0x338, 0x6C8), + MX53_PIN_GPIO_16 = _MXC_BUILD_GPIO_PIN_MX53(6, 11, 1, 0x33C, 0x6CC), + MX53_PIN_GPIO_17 = _MXC_BUILD_GPIO_PIN_MX53(6, 12, 1, 0x340, 0x6D0), + MX53_PIN_GPIO_18 = _MXC_BUILD_GPIO_PIN_MX53(6, 13, 1, 0x344, 0x6D4), + MX53_PIN_NVCC_GPIO = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x6D8), + MX53_PIN_POR_B = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x6DC), + MX53_PIN_BOOT_MODE1 = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x6E0), + MX53_PIN_RESET_IN_B = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x6E4), + MX53_PIN_BOOT_MODE0 = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x6E8), + MX53_PIN_TEST_MODE = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x6EC), + MX53_PIN_GRP_ADDDS = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x6F0), + MX53_PIN_GRP_DDRMODE_CTL = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x6F4), + MX53_PIN_GRP_DDRPKE = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x6FC), + MX53_PIN_GRP_DDRPK = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x708), + MX53_PIN_GRP_TERM_CTL3 = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x70C), + MX53_PIN_GRP_DDRHYS = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x710), + MX53_PIN_GRP_DDRMODE = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x714), + MX53_PIN_GRP_B0DS = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x718), + MX53_PIN_GRP_B1DS = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x71C), + MX53_PIN_GRP_CTLDS = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x720), + MX53_PIN_GRP_DDR_TYPE = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x724), + MX53_PIN_GRP_B2DS = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x728), + MX53_PIN_GRP_B3DS = _MXC_BUILD_NON_GPIO_PIN_MX53(NON_MUX_I, 0x72C), +}; + +/*! + * various IOMUX input select register index + */ +enum iomux_input_select_mx53 { + MUX_IN_AUDMUX_P4_INPUT_DA_AMX_SELECT_I = 0, + MUX_IN_AUDMUX_P4_INPUT_DB_AMX_SELECT_I, + MUX_IN_AUDMUX_P4_INPUT_RXCLK_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P4_INPUT_RXFS_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P5_INPUT_DA_AMX_SELECT_I, + MUX_IN_AUDMUX_P5_INPUT_DB_AMX_SELECT_I, + MUX_IN_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P5_INPUT_RXFS_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT, + MUX_IN_CAN1_IPP_IND_CANRX_SELECT_INPUT, /*0x760*/ + MUX_IN_CAN2_IPP_IND_CANRX_SELECT_INPUT, + MUX_IN_CCM_IPP_ASRC_EXT_SELECT_INPUT, + MUX_IN_CCM_IPP_DI1_CLK_SELECT_INPUT, + MUX_IN_CCM_PLL1_BYPASS_CLK_SELECT_INPUT, + MUX_IN_CCM_PLL2_BYPASS_CLK_SELECT_INPUT, + MUX_IN_CCM_PLL3_BYPASS_CLK_SELECT_INPUT, + MUX_IN_CCM_PLL4_BYPASS_CLK_SELECT_INPUT, + MUX_IN_CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT, /*0x780*/ + MUX_IN_CSPI_IPP_IND_MISO_SELECT_INPUT, + MUX_IN_CSPI_IPP_IND_MOSI_SELECT_INPUT, + MUX_IN_CSPI_IPP_IND_SS_B_1_SELECT_INPUT, + MUX_IN_CSPI_IPP_IND_SS_B_2_SELECT_INPUT, + MUX_IN_CSPI_IPP_IND_SS_B_3_SELECT_INPUT, + MUX_IN_CSPI_IPP_IND_SS_B_4_SELECT_INPUT, + + MUX_IN_ECSPI1_IPP_CSPI_CLK_IN_SELECT_INPUT, + MUX_IN_ECSPI1_IPP_IND_MISO_SELECT_INPUT, + MUX_IN_ECSPI1_IPP_IND_MOSI_SELECT_INPUT, + MUX_IN_ECSPI1_IPP_IND_SS_B_1_SELECT_INPUT, + MUX_IN_ECSPI1_IPP_IND_SS_B_2_SELECT_INPUT, + MUX_IN_ECSPI1_IPP_IND_SS_B_3_SELECT_INPUT, /*0x7B0*/ + MUX_IN_ECSPI1_IPP_IND_SS_B_4_SELECT_INPUT, + MUX_IN_ECSPI2_IPP_CSPI_CLK_IN_SELECT_INPUT, + MUX_IN_ECSPI2_IPP_IND_MISO_SELECT_INPUT, + MUX_IN_ECSPI2_IPP_IND_MOSI_SELECT_INPUT, + MUX_IN_ECSPI2_IPP_IND_SS_B_1_SELECT_INPUT, + MUX_IN_ECSPI2_IPP_IND_SS_B_2_SELECT_INPUT, + MUX_IN_ESAI1_IPP_IND_FSR_SELECT_INPUT, + MUX_IN_ESAI1_IPP_IND_FST_SELECT_INPUT, + MUX_IN_ESAI1_IPP_IND_HCKR_SELECT_INPUT, + MUX_IN_ESAI1_IPP_IND_HCKT_SELECT_INPUT, + MUX_IN_ESAI1_IPP_IND_SCKR_SELECT_INPUT, + MUX_IN_ESAI1_IPP_IND_SCKT_SELECT_INPUT, /*0x7E0*/ + MUX_IN_ESAI1_IPP_IND_SDO0_SELECT_INPUT, + MUX_IN_ESAI1_IPP_IND_SDO1_SELECT_INPUT, + MUX_IN_ESAI1_IPP_IND_SDO2_SDI3_SELECT_INPUT, + MUX_IN_ESAI1_IPP_IND_SDO3_SDI2_SELECT_INPUT, + MUX_IN_ESAI1_IPP_IND_SDO4_SDI1_SELECT_INPUT, + MUX_IN_ESAI1_IPP_IND_SDO5_SDI0_SELECT_INPUT, + MUX_IN_ESDHC1_IPP_WP_ON_SELECT_INPUT, + MUX_IN_FEC_FEC_COL_SELECT_INPUT, /*0x800*/ + MUX_IN_FEC_FEC_MDI_SELECT_INPUT, + MUX_IN_FEC_FEC_RX_CLK_SELECT_INPUT, + MUX_IN_FIRI_IPP_IND_RXD_SELECT_INPUT, + MUX_IN_GPC_PMIC_RDY_SELECT_INPUT, + MUX_IN_I2C1_IPP_SCL_IN_SELECT_INPUT, + MUX_IN_I2C1_IPP_SDA_IN_SELECT_INPUT, + MUX_IN_I2C2_IPP_SCL_IN_SELECT_INPUT, + MUX_IN_I2C2_IPP_SDA_IN_SELECT_INPUT, + MUX_IN_I2C3_IPP_SCL_IN_SELECT_INPUT, + MUX_IN_I2C3_IPP_SDA_IN_SELECT_INPUT, + + MUX_IN_IPU_IPP_DI_0_IND_DISPB_SD_D_SELECT_INPUT, + MUX_IN_IPU_IPP_DI_1_IND_DISPB_SD_D_SELECT_INPUT, + + MUX_IN_IPU_IPP_IND_SENS1_DATA_EN_SELECT_INPUT, + MUX_IN_IPU_IPP_IND_SENS1_HSYNC_SELECT_INPUT, + MUX_IN_IPU_IPP_IND_SENS1_VSYNC_SELECT_INPUT, + + MUX_IN_KPP_IPP_IND_COL_5_SELECT_INPUT, /*0x840*/ + MUX_IN_KPP_IPP_IND_COL_6_SELECT_INPUT, + MUX_IN_KPP_IPP_IND_COL_7_SELECT_INPUT, + MUX_IN_KPP_IPP_IND_ROW_5_SELECT_INPUT, + MUX_IN_KPP_IPP_IND_ROW_6_SELECT_INPUT, + MUX_IN_KPP_IPP_IND_ROW_7_SELECT_INPUT, + + MUX_IN_MLB_MLBCLK_IN_SELECT_INPUT, + MUX_IN_MLB_MLBDAT_IN_SELECT_INPUT, + MUX_IN_MLB_MLBSIG_IN_SELECT_INPUT, + + MUX_IN_OWIRE_BATTERY_LINE_IN_SELECT_INPUT, + + MUX_IN_SDMA_EVENTS_14_SELECT_INPUT, + MUX_IN_SDMA_EVENTS_15_SELECT_INPUT, + + MUX_IN_SPDIF_SPDIF_IN1_SELECT_INPUT, /*0x870*/ + MUX_IN_UART1_IPP_UART_RTS_B_SELECT_INPUT, + MUX_IN_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, + MUX_IN_UART2_IPP_UART_RTS_B_SELECT_INPUT, + MUX_IN_UART2_IPP_UART_RXD_MUX_SELECT_INPUT, + MUX_IN_UART3_IPP_UART_RTS_B_SELECT_INPUT, + MUX_IN_UART3_IPP_UART_RXD_MUX_SELECT_INPUT, + MUX_IN_UART4_IPP_UART_RTS_B_SELECT_INPUT, + MUX_IN_UART4_IPP_UART_RXD_MUX_SELECT_INPUT, + MUX_IN_UART5_IPP_UART_RTS_B_SELECT_INPUT, + MUX_IN_UART5_IPP_UART_RXD_MUX_SELECT_INPUT, + + MUX_IN_USBOH3_IPP_IND_OTG_OC_SELECT_INPUT, + MUX_IN_USBOH3_IPP_IND_UH1_OC_SELECT_INPUT, + MUX_IN_USBOH3_IPP_IND_UH2_OC_SELECT_INPUT, + MUX_INPUT_NUM_MUX, +}; + +#endif /* __ASSEMBLY__ */ +#endif /* __ASM_ARCH_MXC_MX53_PINS_H__ */ diff --git a/arch/arm/mach-mx5/sdma_script_code_mx53.h b/arch/arm/mach-mx5/sdma_script_code_mx53.h new file mode 100644 index 000000000000..25f192d2d19d --- /dev/null +++ b/arch/arm/mach-mx5/sdma_script_code_mx53.h @@ -0,0 +1,193 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ + +/*! + * @file sdma_script_code.h + * @brief This file contains functions of SDMA scripts code initialization + * + * The file was generated automatically. Based on sdma scripts library. + * + * @ingroup SDMA + */ +/************************************************************************************ + + SDMA RELEASE LABEL: "SDMA_RITA.01.00.00" + +*************************************************************************************/ + +#ifndef __SDMA_SCRIPT_CODE_MX53_H__ +#define __SDMA_SCRIPT_CODE_MX53_H__ + +/*! +* SDMA ROM scripts start addresses and sizes +*/ + +#define start_ADDR_MX53 0 +#define start_SIZE_MX53 22 + +#define core_ADDR_MX53 80 +#define core_SIZE_MX53 232 + +#define common_ADDR_MX53 312 +#define common_SIZE_MX53 330 + +#define ap_2_ap_ADDR_MX53 642 +#define ap_2_ap_SIZE_MX53 41 + +#define app_2_mcu_ADDR_MX53 683 +#define app_2_mcu_SIZE_MX53 64 + +#define mcu_2_app_ADDR_MX53 747 +#define mcu_2_app_SIZE_MX53 70 + +#define uart_2_mcu_ADDR_MX53 817 +#define uart_2_mcu_SIZE_MX53 74 + +#define shp_2_mcu_ADDR_MX53 891 +#define shp_2_mcu_SIZE_MX53 69 + +#define mcu_2_shp_ADDR_MX53 960 +#define mcu_2_shp_SIZE_MX53 72 + +#define uartsh_2_mcu_ADDR_MX53 1032 +#define uartsh_2_mcu_SIZE_MX53 68 + +#define spdif_2_mcu_ADDR_MX53 1100 +#define spdif_2_mcu_SIZE_MX53 34 + +#define mcu_2_spdif_ADDR_MX53 1134 +#define mcu_2_spdif_SIZE_MX53 59 + +#define firi_2_mcu_ADDR_MX53 1193 +#define firi_2_mcu_SIZE_MX53 97 + +#define mcu_2_firi_ADDR_MX53 1290 +#define mcu_2_firi_SIZE_MX53 79 + +#define loop_DMAs_routines_ADDR_MX53 1369 +#define loop_DMAs_routines_SIZE_MX53 227 + +#define test_ADDR_MX53 1596 +#define test_SIZE_MX53 63 + +#define signature_ADDR_MX53 1023 +#define signature_SIZE_MX53 1 + +/*! +* SDMA RAM scripts start addresses and sizes +*/ + +#define asrc__mcu_ADDR_MX53 6144 +#define asrc__mcu_SIZE_MX53 114 + +#define mcu_2_ssiapp_ADDR_MX53 6258 +#define mcu_2_ssiapp_SIZE_MX53 96 + +#define p_2_p_ADDR_MX53 6354 +#define p_2_p_SIZE_MX53 254 + +#define ssiapp_2_mcu_ADDR_MX53 6608 +#define ssiapp_2_mcu_SIZE_MX53 93 + +/*! +* SDMA RAM image start address and size +*/ + +#define RAM_CODE_START_ADDR_MX53 6144 +#define RAM_CODE_SIZE_MX53 557 + +/*! +* Buffer that holds the SDMA RAM image +*/ +__attribute__ ((__aligned__(4))) +#ifndef CONFIG_XIP_KERNEL +const +#endif +static const short sdma_code_mx53[] = { + 0xc1d9, 0xc1e3, 0x56f3, 0x57db, 0x047a, 0x7d07, 0x072f, 0x076e, + 0x7d02, 0x6ec7, 0x9813, 0x6ed7, 0x9813, 0x074f, 0x076e, 0x7d02, + 0x6e01, 0x9813, 0x6e05, 0x5ce3, 0x048f, 0x0410, 0x3c0f, 0x5c93, + 0x0eff, 0x06bf, 0x06d5, 0x7d01, 0x068d, 0x05a6, 0x5deb, 0x55fb, + 0x008e, 0x0768, 0x7d02, 0x0769, 0x7c04, 0x06d4, 0x7d01, 0x008c, + 0x04a0, 0x06a0, 0x076f, 0x7d0c, 0x076e, 0x7d05, 0x7802, 0x62c8, + 0x5a05, 0x7c2b, 0x9845, 0x7802, 0x5205, 0x6ac8, 0x7c26, 0x9845, + 0x076e, 0x7d05, 0x7802, 0x620b, 0x5a05, 0x7c21, 0x9845, 0x7802, + 0x5205, 0x6a0b, 0x7c1c, 0x6a28, 0x7f1a, 0x0768, 0x7d02, 0x0769, + 0x7c0a, 0x4c00, 0x7c08, 0x0768, 0x7d03, 0x5a05, 0x7f11, 0x9852, + 0x5205, 0x7e0e, 0x5493, 0x4e00, 0x7ccb, 0x0000, 0x54e3, 0x55eb, + 0x4d00, 0x7d0a, 0xc1fa, 0x57db, 0x9814, 0x68cc, 0x9860, 0x680c, + 0x009e, 0x0007, 0x54e3, 0xd866, 0xc20a, 0x9802, 0x55eb, 0x009d, + 0x058c, 0x0aff, 0x0211, 0x1aff, 0x05ba, 0x05a0, 0x04b2, 0x04ad, + 0x0454, 0x0006, 0xc1e3, 0x57db, 0x52f3, 0x6a01, 0x008f, 0x00d5, + 0x7d01, 0x008d, 0x05a0, 0x5deb, 0x0478, 0x7d03, 0x0479, 0x7d2c, + 0x7c36, 0x0479, 0x7c1f, 0x56ee, 0x0f00, 0x0660, 0x7d05, 0x6509, + 0x7e43, 0x620a, 0x7e41, 0x9890, 0x620a, 0x7e3e, 0x6509, 0x7e3c, + 0x0512, 0x0512, 0x02ad, 0x0760, 0x7d03, 0x55fb, 0x6dd3, 0x989b, + 0x55fb, 0x1d04, 0x6dd3, 0x6ac8, 0x7f2f, 0x1f01, 0x2003, 0x4800, + 0x7ce4, 0x98c3, 0x55fb, 0x6dd7, 0x0015, 0x7805, 0x6209, 0x6ac8, + 0x6209, 0x6ac8, 0x6dd7, 0x98c2, 0x55fb, 0x6dd7, 0x0015, 0x0015, + 0x7805, 0x620a, 0x6ac8, 0x620a, 0x6ac8, 0x6dd7, 0x98c2, 0x55fb, + 0x6dd7, 0x0015, 0x0015, 0x0015, 0x7805, 0x620b, 0x6ac8, 0x620b, + 0x6ac8, 0x6dd7, 0x7c09, 0x6ddf, 0x7f07, 0x0000, 0x55eb, 0x4d00, + 0x7d07, 0xc1fa, 0x57db, 0x9876, 0x0007, 0x68cc, 0x680c, 0xc213, + 0xc20a, 0x9873, 0x0b70, 0x0311, 0x5313, 0x076c, 0x7c01, 0xc1d9, + 0x5efb, 0x068a, 0x076b, 0x7c01, 0xc1d9, 0x5ef3, 0x59db, 0x58d3, + 0x018f, 0x0110, 0x390f, 0x008b, 0xc13c, 0x7d2b, 0x5ac0, 0x5bc8, + 0xc14e, 0x7c27, 0x0388, 0x0689, 0x5ce3, 0x0dff, 0x0511, 0x1dff, + 0x05bc, 0x073e, 0x4d00, 0x7d18, 0x0870, 0x0011, 0x077e, 0x7d09, + 0x077d, 0x7d02, 0x5228, 0x98fd, 0x52f8, 0x54db, 0x02bc, 0x02cc, + 0x7c09, 0x077c, 0x7d02, 0x5228, 0x9906, 0x52f8, 0x54d3, 0x02bc, + 0x02cc, 0x7d09, 0x0400, 0x98f4, 0x008b, 0x52c0, 0x53c8, 0xc159, + 0x7dd6, 0x0200, 0x98e4, 0x08ff, 0x00bf, 0x077f, 0x7d15, 0x0488, + 0x00d5, 0x7d01, 0x008d, 0x05a0, 0x5deb, 0x028f, 0x0212, 0x0212, + 0x3aff, 0x05da, 0x7c02, 0x073e, 0x992f, 0x02a4, 0x02dd, 0x7d02, + 0x073e, 0x992f, 0x075e, 0x992f, 0x55eb, 0x0598, 0x5deb, 0x52f3, + 0x54fb, 0x076a, 0x7d26, 0x076c, 0x7d01, 0x996c, 0x076b, 0x7c57, + 0x0769, 0x7d04, 0x0768, 0x7d02, 0x0e01, 0x9946, 0x5893, 0x00d6, + 0x7d01, 0x008e, 0x5593, 0x05a0, 0x5d93, 0x06a0, 0x7802, 0x5502, + 0x5d04, 0x7c1d, 0x4e00, 0x7c08, 0x0769, 0x7d03, 0x5502, 0x7e17, + 0x9953, 0x5d04, 0x7f14, 0x0689, 0x5093, 0x4800, 0x7d01, 0x993e, + 0x99b7, 0x0015, 0x7806, 0x5502, 0x5d04, 0x074f, 0x5502, 0x5d24, + 0x072f, 0x7c01, 0x99b7, 0x0017, 0x076f, 0x7c01, 0x2001, 0x5593, + 0x009d, 0x0007, 0xd9be, 0x990c, 0x6cd3, 0x0769, 0x7d04, 0x0768, + 0x7d02, 0x0e01, 0x997b, 0x5893, 0x00d6, 0x7d01, 0x008e, 0x5593, + 0x05a0, 0x5d93, 0x06a0, 0x7802, 0x5502, 0x6dc8, 0x7c0f, 0x4e00, + 0x7c08, 0x0769, 0x7d03, 0x5502, 0x7e09, 0x9988, 0x6dc8, 0x7f06, + 0x0689, 0x5093, 0x4800, 0x7d01, 0x9973, 0x99b7, 0x99b1, 0x6ac3, + 0x0769, 0x7d04, 0x0768, 0x7d02, 0x0e01, 0x999e, 0x5893, 0x00d6, + 0x7d01, 0x008e, 0x5593, 0x05a0, 0x5d93, 0x06a0, 0x7802, 0x65c8, + 0x5d04, 0x7c0f, 0x4e00, 0x7c08, 0x0769, 0x7d03, 0x65c8, 0x7e09, + 0x99ab, 0x5d04, 0x7f06, 0x0689, 0x5093, 0x4800, 0x7d01, 0x9996, + 0x99b7, 0x5593, 0x009d, 0x0007, 0x6cff, 0xd9be, 0x990c, 0x0000, + 0x54e3, 0x55eb, 0x4d00, 0x7c01, 0x990c, 0x98f4, 0x54e3, 0x55eb, + 0x0aff, 0x0211, 0x1aff, 0x077f, 0x7c02, 0x05a0, 0x99cb, 0x009d, + 0x058c, 0x05ba, 0x05a0, 0x0210, 0x04ba, 0x04ad, 0x0454, 0x0006, + 0xc1e3, 0x57db, 0x52fb, 0x6ac3, 0x52f3, 0x6a05, 0x008f, 0x00d5, + 0x7d01, 0x008d, 0x05a0, 0x5deb, 0x0478, 0x7d03, 0x0479, 0x7d2b, + 0x7c1e, 0x0479, 0x7c33, 0x56ee, 0x0f00, 0x55fb, 0x0760, 0x7d02, + 0x6dc3, 0x99ec, 0x1d04, 0x6dc3, 0x62c8, 0x7e3b, 0x0660, 0x7d02, + 0x0210, 0x0212, 0x6a09, 0x7f35, 0x0212, 0x6a09, 0x7f32, 0x0212, + 0x6a09, 0x7f2f, 0x1f01, 0x2003, 0x4800, 0x7ce7, 0x9a20, 0x55fb, + 0x6dc7, 0x0015, 0x0015, 0x0015, 0x7805, 0x62c8, 0x6a0b, 0x62c8, + 0x6a0b, 0x6dc7, 0x9a1f, 0x55fb, 0x6dc7, 0x0015, 0x0015, 0x7805, + 0x62c8, 0x6a0a, 0x62c8, 0x6a0a, 0x6dc7, 0x9a1f, 0x55fb, 0x6dc7, + 0x0015, 0x7805, 0x62c8, 0x6a09, 0x62c8, 0x6a09, 0x6dc7, 0x7c09, + 0x6a28, 0x7f07, 0x0000, 0x55eb, 0x4d00, 0x7d05, 0xc1fa, 0x57db, + 0x99d6, 0xc277, 0x0454, 0xc20a, 0x99d1 +}; +#endif diff --git a/arch/arm/mach-mx5/serial.c b/arch/arm/mach-mx5/serial.c index d0ac961b2637..1c0b2c0f4e9e 100644 --- a/arch/arm/mach-mx5/serial.c +++ b/arch/arm/mach-mx5/serial.c @@ -23,7 +23,7 @@ #include <mach/hardware.h> #include <mach/mxc_uart.h> #include "serial.h" -#include "board-mx51_3stack.h" +#include "board-mx53_evk.h" #if defined(CONFIG_SERIAL_MXC) || defined(CONFIG_SERIAL_MXC_MODULE) @@ -110,6 +110,56 @@ static uart_mxc_port mxc_ports[] = { .dma_rx_id = MXC_DMA_UART3_RX, .rxd_mux = MXC_UART_RXDMUX, }, + [3] = { + .port = { + .membase = (void *)IO_ADDRESS(UART4_BASE_ADDR), + .mapbase = UART4_BASE_ADDR, + .iotype = SERIAL_IO_MEM, + .irq = UART4_INT1, + .fifosize = 32, + .flags = ASYNC_BOOT_AUTOCONF, + .line = 3, + }, + .ints_muxed = UART4_MUX_INTS, + .irqs = {UART4_INT2, UART4_INT3}, + .mode = UART4_MODE, + .ir_mode = UART4_IR, + .enabled = UART4_ENABLED, + .hardware_flow = UART4_HW_FLOW, + .cts_threshold = UART4_UCR4_CTSTL, + .dma_enabled = UART4_DMA_ENABLE, + .dma_rxbuf_size = UART4_DMA_RXBUFSIZE, + .rx_threshold = UART4_UFCR_RXTL, + .tx_threshold = UART4_UFCR_TXTL, + .dma_tx_id = MXC_DMA_UART4_TX, + .dma_rx_id = MXC_DMA_UART4_RX, + .rxd_mux = MXC_UART_RXDMUX, + }, + [4] = { + .port = { + .membase = (void *)IO_ADDRESS(UART5_BASE_ADDR), + .mapbase = UART5_BASE_ADDR, + .iotype = SERIAL_IO_MEM, + .irq = UART5_INT1, + .fifosize = 32, + .flags = ASYNC_BOOT_AUTOCONF, + .line = 4, + }, + .ints_muxed = UART5_MUX_INTS, + .irqs = {UART5_INT2, UART5_INT3}, + .mode = UART5_MODE, + .ir_mode = UART5_IR, + .enabled = UART5_ENABLED, + .hardware_flow = UART5_HW_FLOW, + .cts_threshold = UART5_UCR4_CTSTL, + .dma_enabled = UART5_DMA_ENABLE, + .dma_rxbuf_size = UART5_DMA_RXBUFSIZE, + .rx_threshold = UART5_UFCR_RXTL, + .tx_threshold = UART5_UFCR_TXTL, + .dma_tx_id = MXC_DMA_UART5_TX, + .dma_rx_id = MXC_DMA_UART5_RX, + .rxd_mux = MXC_UART_RXDMUX, + }, }; static struct platform_device mxc_uart_device1 = { @@ -136,15 +186,46 @@ static struct platform_device mxc_uart_device3 = { }, }; +static struct platform_device mxc_uart_device4 = { + .name = "mxcintuart", + .id = 3, + .dev = { + .platform_data = &mxc_ports[3], + }, +}; + +static struct platform_device mxc_uart_device5 = { + .name = "mxcintuart", + .id = 4, + .dev = { + .platform_data = &mxc_ports[4], + }, +}; + static int __init mxc_init_uart(void) { + int i; + + if (cpu_is_mx53()) { + for (i = 0; i < ARRAY_SIZE(mxc_ports); i++) { + mxc_ports[i].port.mapbase -= 0x20000000; + } + } + /* Register all the MXC UART platform device structures */ platform_device_register(&mxc_uart_device1); platform_device_register(&mxc_uart_device2); #if UART3_ENABLED == 1 platform_device_register(&mxc_uart_device3); #endif /* UART3_ENABLED */ - + if (cpu_is_mx53()) { +#if UART4_ENABLED == 1 + platform_device_register(&mxc_uart_device4); +#endif /* UART4_ENABLED */ +#if UART5_ENABLED == 1 + platform_device_register(&mxc_uart_device5); +#endif /* UART5_ENABLED */ + } return 0; } diff --git a/arch/arm/mach-mx5/serial.h b/arch/arm/mach-mx5/serial.h index c2eb9fa29419..aa97228e3865 100644 --- a/arch/arm/mach-mx5/serial.h +++ b/arch/arm/mach-mx5/serial.h @@ -69,6 +69,20 @@ #define UART3_DMA_RXBUFSIZE 1024 #define UART3_UFCR_RXTL 16 #define UART3_UFCR_TXTL 16 +/* UART 4 configuration */ +#define UART4_HW_FLOW 0 +#define UART4_UCR4_CTSTL -1 +#define UART4_DMA_ENABLE 0 +#define UART4_DMA_RXBUFSIZE 512 +#define UART4_UFCR_RXTL 16 +#define UART4_UFCR_TXTL 16 +/* UART 5 configuration */ +#define UART5_HW_FLOW 0 +#define UART5_UCR4_CTSTL -1 +#define UART5_DMA_ENABLE 0 +#define UART5_DMA_RXBUFSIZE 512 +#define UART5_UFCR_RXTL 16 +#define UART5_UFCR_TXTL 16 /* * UART Chip level Configuration that a user may not have to edit. These * configuration vary depending on how the UART module is integrated with @@ -115,5 +129,15 @@ #define UART3_INT1 MXC_INT_UART3 #define UART3_INT2 -1 #define UART3_INT3 -1 +/* UART 4 configuration */ +#define UART4_MUX_INTS INTS_MUXED +#define UART4_INT1 MXC_INT_UART4 +#define UART4_INT2 -1 +#define UART4_INT3 -1 +/* UART 5 configuration */ +#define UART5_MUX_INTS INTS_MUXED +#define UART5_INT1 MXC_INT_UART5 +#define UART5_INT2 -1 +#define UART5_INT3 -1 #endif /* __ARCH_ARM_MACH_MX51_SERIAL_H__ */ |