ccwmx51: Fix compilation issues after applying Freescale patches

The mach-mx51 folder has been replaced by mach-mx5 to enable the addition
of more platforms.

Signed-off-by: Alejandro Gonzalez <alex.gonzalez@digi.com>

15 files changed, 2195 insertions, 10 deletions

diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig
index 5c07a3a5d2b6..cd6a985af260 100644
--- a/arch/arm/mach-mx5/Kconfig
+++ b/arch/arm/mach-mx5/Kconfig
@@ -1,10 +1,10 @@
 if ARCH_MX5
 
 config ARCH_MX51
-	bool
+	bool "MX51"
 
 config ARCH_MX53
-	bool
+	bool "MX53"
 
 config FORCE_MAX_ZONEORDER
     int "MAX_ORDER"
@@ -44,6 +44,25 @@ config MACH_MX53_EVK
 	  Include support for MX53 EVK platform. This includes specific
 	  configurations for the board and its peripherals.
 
+config MODULE_CCXMX51
+	bool
+
+config MACH_CCWMX51JS
+	bool "Support for the ConnectCore Wi-i.MX51 module, on the JSK base board"
+	select MODULE_CCXMX51
+	help
+	  Include support for the Digi ConnectCore Wi-i.MX51 Embedded Module, on the
+	  JumpStart Kit base board. This includes specific configurations for the
+	  peripherals on that base board.
+
+config MACH_CCWMX51
+	bool "Support for the ConnectCore Wi-i.MX51 module"
+	select MODULE_CCXMX51
+	help
+	  Include support for the Digi ConnectCore Wi-i.MX51 Embedded Module, on a
+	  custom board. The machine file should be modified to include support for
+	  the interfaces available in that board.
+
 comment "MX5x Options:"
 
 config MXC_SDMA_API
@@ -76,3 +95,58 @@ config SDMA_IRAM
 	  Support Internal RAM as SDMA buffer or control structures
 
 endif
+
+menu "Serial Port Options"
+config UART1_ENABLED
+	bool "Enable UART1"
+	default y
+	depends on SERIAL_MXC && MACH_CCWMX51JS
+	help
+	  Enable the MX51 UART1 interface
+
+config UART2_ENABLED
+	bool "Enable UART2"
+	default y
+	depends on SERIAL_MXC && MACH_CCWMX51JS
+	help
+	  Enable the MX51 UART2 interface
+
+config UART3_ENABLED
+	bool "Enable UART3"
+	default y
+	depends on SERIAL_MXC && MACH_CCWMX51JS
+	help
+	  Enable the MX51 UART3 interface
+endmenu
+
+menu "SPI Interface Options"
+config SPI_MXC_SELECT1
+	bool "Enable CSPI1"
+	depends on SPI_MXC && MACH_CCWMX51JS
+	default y
+	help
+	  Enable the CSPI1 interface
+
+config SPI_MXC_SELECT1_SS1
+	bool "Enable SS1 line for CSPI1"
+	depends on SPI_MXC_SELECT1 && MACH_CCWMX51JS
+	default y
+	help
+          Enable SS1 (slave select 1) line, used on ConnectCore Wi-i.MX51 base board SPI connector
+
+config SPI_MXC_SELECT2
+	bool "Enable CSPI2"
+	depends on SPI_MXC && MACH_CCWMX51JS
+	default n
+	help
+	  Enable the CSPI2 interface
+
+config SPI_MXC_SELECT3
+	bool "Enable CSPI3"
+	depends on SPI_MXC && MACH_CCWMX51JS
+	default n
+	help
+	  Enable the CSPI3 interface
+endmenu
+
+source "arch/arm/mach-mx5/displays/Kconfig"
\ No newline at end of file
diff --git a/arch/arm/mach-mx5/Makefile b/arch/arm/mach-mx5/Makefile
index cbf2137fd938..a04f5017b6d0 100644
--- a/arch/arm/mach-mx5/Makefile
+++ b/arch/arm/mach-mx5/Makefile
@@ -11,4 +11,5 @@ sdram_autogating.o bus_freq.o usb_dr.o usb_h1.o usb_h2.o dummy_gpio.o wfi.o susp
 obj-$(CONFIG_MACH_MX51_3DS) += mx51_3stack.o mx51_3stack_gpio.o mx51_3stack_pmic_mc13892.o
 obj-$(CONFIG_MACH_MX51_BABBAGE) += mx51_babbage.o mx51_babbage_gpio.o mx51_babbage_pmic_mc13892.o
 obj-$(CONFIG_MACH_MX53_EVK) += mx53_evk.o mx53_evk_gpio.o mx53_evk_pmic_mc13892.o
-
+obj-$(CONFIG_MACH_CCWMX51JS) += mx51_ccwmx51js.o mx51_ccwmx51js_gpio.o
+obj-$(CONFIG_MXC_PMIC_MC13892) +=  mx51_ccwmx51js_pmic_mc13892.o
diff --git a/arch/arm/mach-mx5/board-ccwmx51.h b/arch/arm/mach-mx5/board-ccwmx51.h
new file mode 100644
index 000000000000..6696c27c5c36
--- /dev/null
+++ b/arch/arm/mach-mx5/board-ccwmx51.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright 2010 Digi International, Inc. All Rights Reserved.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#ifndef __ASM_ARCH_MXC_BOARD_CCWMX51_H__
+#define __ASM_ARCH_MXC_BOARD_CCWMX51_H__
+
+#include <mach/mxc_uart.h>
+
+/* UART 1 configuration */
+#if defined CONFIG_UART1_ENABLED
+#define UART1_ENABLED		1
+#else
+#define UART1_ENABLED		0
+#endif
+#define UART1_MODE		MODE_DCE
+#define UART1_IR		NO_IRDA
+
+/* UART 2 configuration */
+#if defined CONFIG_UART2_ENABLED
+#define UART2_ENABLED		1
+#else
+#define UART2_ENABLED		0
+#endif
+#define UART2_MODE		MODE_DCE
+#define UART2_IR		NO_IRDA
+
+/* UART 3 configuration */
+#if defined CONFIG_UART3_ENABLED
+#define UART3_ENABLED		1
+#else
+#define UART3_ENABLED		0
+#endif
+#define UART3_MODE		MODE_DCE
+#define UART3_IR		NO_IRDA
+
+/*!
+ * Specifies if the Irda transmit path is inverting
+ */
+#define MXC_IRDA_TX_INV	0
+/*!
+ * Specifies if the Irda receive path is inverting
+ */
+#define MXC_IRDA_RX_INV	0
+
+#define MXC_LL_UART_PADDR	UART1_BASE_ADDR
+#define MXC_LL_UART_VADDR	AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
+
+#endif		/* __ASM_ARCH_MXC_BOARD_CCWMX51_H__ */
diff --git a/arch/arm/mach-mx5/devices.c b/arch/arm/mach-mx5/devices.c
index df433a8f5417..143ba48d2b2c 100644
--- a/arch/arm/mach-mx5/devices.c
+++ b/arch/arm/mach-mx5/devices.c
@@ -258,6 +258,13 @@ struct platform_device mxc_fb_devices[] = {
 	},
 };
 
+struct platform_device lcd_pdev = {
+        .name = "ccwmx51_display",
+        .dev = {
+                .coherent_dma_mask = DMA_BIT_MASK(32),
+        },
+};
+
 static struct resource vpu_resources[] = {
 	{
 		.start = VPU_BASE_ADDR,
@@ -610,6 +617,70 @@ struct mxc_gpio_port mxc_gpio_ports[] = {
 	},
 };
 
+#if defined(CONFIG_SMSC9118) || defined(CONFIG_SMSC9118_MODULE)
+static struct resource smsc911x_device_resources[] = {
+	{
+		.name	= "smsc911x-memory",
+		.start	= CS5_BASE_ADDR,
+		.end	= CS5_BASE_ADDR + SZ_4K - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	{
+		.start	= IOMUX_TO_IRQ(MX51_PIN_GPIO1_9),
+		.end	= IOMUX_TO_IRQ(MX51_PIN_GPIO1_9),
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+static struct platform_device smsc911x_device = {
+        .name             = "smsc911x",
+        .id               = -1,
+        .num_resources    = ARRAY_SIZE(smsc911x_device_resources),
+        .resource         = smsc911x_device_resources,
+};
+
+/* WEIM registers */
+#define CSGCR1	0x00
+#define CSGCR2	0x04
+#define CSRCR1	0x08
+#define CSRCR2	0x0C
+#define CSWCR1	0x10
+
+static void ccwmx51_init_ext_eth_mac(void)
+{
+	__iomem u32 *weim_vbaddr;
+
+	weim_vbaddr = ioremap(WEIM_BASE_ADDR, SZ_4K);
+	if (weim_vbaddr == 0) {
+		printk(KERN_ERR "Unable to ioremap 0x%08x in %s\n", WEIM_BASE_ADDR, __func__);
+		return;
+	}
+
+	/** Configure the CS timming, bus width, etc.
+	 * 16 bit on DATA[31..16], not multiplexed, async
+	 * RWSC=50, RADVA=2, RADVN=6, OEA=0, OEN=0, RCSA=0, RCSN=0, APR=0
+	 * WAL=0, WBED=1, WWSC=50, WADVA=2, WADVN=6, WEA=0, WEN=0, WCSA=0
+	 */
+	writel(0x00420081, (unsigned int)(weim_vbaddr) + 0x78 + CSGCR1);
+	writel(0, (unsigned int)(weim_vbaddr) + 0x78 + CSGCR2);
+	writel(0x32260000, (unsigned int)(weim_vbaddr) + 0x78 + CSRCR1);
+	writel(0, (unsigned int)(weim_vbaddr) + 0x78 + CSRCR2);
+	writel(0x72080f00, (unsigned int)(weim_vbaddr) + 0x78 + CSWCR1);
+
+	iounmap(weim_vbaddr);
+
+	/* Configure interrupt line as GPIO input, the iomux should be already setup */
+	gpio_request(IOMUX_TO_GPIO(MX51_PIN_GPIO1_9), "LAN2-irq");
+	gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_9));
+}
+#endif
+
+#if defined(CONFIG_SND_SOC_IMX_CCWMX51_WM8753) || defined(CONFIG_SND_SOC_IMX_CCWMX51_WM8753_MODULE)
+struct platform_device mxc_wm8753_device = {
+	.name = "ccwmx51js",
+};
+#endif
+
 int __init mxc_register_gpios(void)
 {
 	if (cpu_is_mx51())
@@ -1346,6 +1417,9 @@ int __init mxc_init_devices(void)
 
 	mxc_init_scc_iram();
 	mxc_init_gpu2d();
+#if defined(CONFIG_SMSC9118) || defined(CONFIG_SMSC9118_MODULE)
+	ccwmx51_init_ext_eth_mac();
+#endif
 	return 0;
 }
 postcore_initcall(mxc_init_devices);
diff --git a/arch/arm/mach-mx5/devices.h b/arch/arm/mach-mx5/devices.h
index d3467faf90e1..e5effff9cedc 100644
--- a/arch/arm/mach-mx5/devices.h
+++ b/arch/arm/mach-mx5/devices.h
@@ -59,4 +59,5 @@ extern struct platform_device mxc_usbdr_otg_device;
 extern struct platform_device mxc_usbdr_host_device;
 extern struct platform_device mxc_usbh1_device;
 extern struct platform_device mxc_usbh2_device;
-
+extern struct platform_device lcd_pdev;
+extern struct platform_device mxc_wm8753_device;
diff --git a/arch/arm/mach-mx5/displays/CUSTOM.h b/arch/arm/mach-mx5/displays/CUSTOM.h
new file mode 100644
index 000000000000..19759533d84e
--- /dev/null
+++ b/arch/arm/mach-mx5/displays/CUSTOM.h
@@ -0,0 +1,34 @@
+
+// static void lcd_bl_enable_custom(int enable)
+// {
+// 	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_DI1_PIN11), enable);
+// }
+// 
+// static struct fb_videomode cusom = {
+// 	.name = "CUSTOM",
+// 	.refresh = ,
+// 	.xres = ,
+// 	.yres = ,
+// 	.pixclock = ,
+// 	.left_margin = ,
+// 	.right_margin = ,
+// 	.upper_margin = ,
+// 	.lower_margin = ,
+// 	.hsync_len = ,
+// 	.vsync_len = ,
+// 	.sync = FB_SYNC_CLK_LAT_FALL,
+// 	.vmode = FB_VMODE_NONINTERLACED,
+// 	.flag = 0,
+// };
+// 
+// #define CUSTOM_DISPLAY				\
+// {							\
+// 	.fb_pdata = {					\
+// 		.interface_pix_fmt = IPU_PIX_FMT_RGB24,	\
+// 		.mode_str = "CUSTOM",			\
+// 		.mode = &custom,			\
+// 	},						\
+// 	.bl_enable = &lcd_bl_enable_custom,		\
+// }
+
+
diff --git a/arch/arm/mach-mx5/displays/Kconfig b/arch/arm/mach-mx5/displays/Kconfig
new file mode 100644
index 000000000000..674a6651bcca
--- /dev/null
+++ b/arch/arm/mach-mx5/displays/Kconfig
@@ -0,0 +1,21 @@
+# arch/arm/mach-mx51/displays/Kconfig
+#
+# Copyright 2010 Digi International, Inc
+#
+
+if FB_MXC_SYNC_PANEL && MACH_CCWMX51JS
+
+comment "Display selection"
+
+config CCWMX51_LQ070Y3DG3B
+	bool "LQ070Y3DG3B TFT LCD support"
+	help
+	  This enables the support for the LQ070Y3DG3B TFT display.
+
+config CCWMX51_CUSTOM
+	bool "Custom display support"
+	help
+	  This enables the support for a customer specific display.
+	  displays/CUSTOM.h has to be modified when selecting this.
+
+endif
diff --git a/arch/arm/mach-mx5/displays/LQ070Y3DG3B.h b/arch/arm/mach-mx5/displays/LQ070Y3DG3B.h
new file mode 100644
index 000000000000..8cf33b65fd6b
--- /dev/null
+++ b/arch/arm/mach-mx5/displays/LQ070Y3DG3B.h
@@ -0,0 +1,31 @@
+
+static void lcd_bl_enable_lq70(int enable)
+{
+	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_DI1_PIN11), enable);
+}
+
+static struct fb_videomode lq70y3dg3b = {
+	.name = "LQ070Y3DG3B",
+	.refresh = 60,
+	.xres = 800,
+	.yres = 480,
+	.pixclock = 33000,
+	.left_margin = 0,
+	.right_margin = 50,
+	.upper_margin = 25,
+	.lower_margin = 10,
+	.hsync_len = 128,
+	.vsync_len = 10,
+	.vmode = FB_VMODE_NONINTERLACED,
+	.flag = 0,
+};
+
+#define LQ070Y3DG3B_DISPLAY				\
+{							\
+	.fb_pdata = {					\
+		.interface_pix_fmt = IPU_PIX_FMT_RGB24,	\
+		.mode_str = "LQ070Y3DG3B",		\
+		.mode = &lq70y3dg3b,			\
+	},						\
+	.bl_enable = &lcd_bl_enable_lq70,		\
+}
diff --git a/arch/arm/mach-mx5/displays/display-ccwmx51.h b/arch/arm/mach-mx5/displays/display-ccwmx51.h
new file mode 100644
index 000000000000..b1e875c9694f
--- /dev/null
+++ b/arch/arm/mach-mx5/displays/display-ccwmx51.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright 2010 Digi International, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_MXC_BOARD_CCWMX51_H__
+#define __ASM_ARCH_MXC_BOARD_CCWMX51_H__
+
+// #include <mach/hardware.h>
+// #include <mach/mxc.h>
+// 
+// struct ccwmx51_lcd_pdata {
+// 	int vinf;
+// 	struct mxc_fb_platform_data fb_pdata;
+// 	void (*reset) (void);
+// 	void (*bl_enable) (int);
+// };
+
+#endif /* __ASM_ARCH_MXC_BOARD_CCWMX51_H__ */
diff --git a/arch/arm/mach-mx5/displays/displays.h b/arch/arm/mach-mx5/displays/displays.h
new file mode 100644
index 000000000000..1fa2c1d05b5d
--- /dev/null
+++ b/arch/arm/mach-mx5/displays/displays.h
@@ -0,0 +1,31 @@
+/*
+ * arch/arm/mach-s3c2443/displays/displays.h
+ *
+ * Copyright (C) 2009 by Digi International Inc.
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_MXC_CCWMX51_DISPLAYS_H__
+#define __ASM_ARCH_MXC_CCWMX51_DISPLAYS_H__
+
+#if defined(CONFIG_CCWMX51_LQ070Y3DG3B)
+#include "LQ070Y3DG3B.h"
+#endif
+#if defined(CONFIG_CCWMX51_CUSTOM)
+#include "CUSTOM.h"
+#endif
+
+struct ccwmx51_lcd_pdata lcd_display_list[] = {
+#if defined(CONFIG_CCWMX51_LQ070Y3DG3B)
+	LQ070Y3DG3B_DISPLAY,
+#endif
+#if defined(CONFIG_CCWMX51_CUSTOM)
+	CUSTOM_DISPLAY,
+#endif
+};
+
+#endif /* __ASM_ARCH_MXC_CCWMX51_DISPLAYS_H__ */
diff --git a/arch/arm/mach-mx5/dummy_gpio.c b/arch/arm/mach-mx5/dummy_gpio.c
index 8d9537d31026..8eb771d29a06 100644
--- a/arch/arm/mach-mx5/dummy_gpio.c
+++ b/arch/arm/mach-mx5/dummy_gpio.c
@@ -14,12 +14,6 @@
 #include <linux/errno.h>
 #include <linux/module.h>
 
-void gpio_uart_active(int port, int no_irda) {}
-EXPORT_SYMBOL(gpio_uart_active);
-
-void gpio_uart_inactive(int port, int no_irda) {}
-EXPORT_SYMBOL(gpio_uart_inactive);
-
 void gpio_gps_active(void) {}
 EXPORT_SYMBOL(gpio_gps_active);
 
diff --git a/arch/arm/mach-mx5/mx51_ccwmx51js.c b/arch/arm/mach-mx5/mx51_ccwmx51js.c
new file mode 100644
index 000000000000..91ccc1dc81f5
--- /dev/null
+++ b/arch/arm/mach-mx5/mx51_ccwmx51js.c
@@ -0,0 +1,660 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2009 - 2010 Digi International, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/types.h>
+#include <linux/sched.h>
+#include <linux/delay.h>
+#include <linux/pm.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/init.h>
+#include <linux/input.h>
+#include <linux/nodemask.h>
+#include <linux/clk.h>
+#include <linux/platform_device.h>
+#include <linux/fsl_devices.h>
+#include <linux/spi/spi.h>
+#include <linux/i2c.h>
+#include <linux/ata.h>
+#include <linux/regulator/consumer.h>
+#include <linux/pmic_external.h>
+#include <linux/pmic_status.h>
+#include <linux/ipu.h>
+#include <linux/mxcfb.h>
+#include <linux/pwm_backlight.h>
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include <asm/irq.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <mach/memory.h>
+#include <mach/gpio.h>
+#include <mach/mmc.h>
+#include <mach/mxc_dvfs.h>
+#include "board-ccwmx51.h"
+#include "iomux.h"
+#include "crm_regs.h"
+#include "devices.h"
+#include "mx51_pins.h"
+#include "displays/displays.h"
+#include <linux/smc911x.h>
+
+#if defined(CONFIG_MTD) || defined(CONFIG_MTD_MODULE)
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/map.h>
+#include <linux/mtd/partitions.h>
+#include <asm/mach/flash.h>
+#endif
+
+extern void __init ccwmx51_io_init(void);
+extern int __init ccwmx51_init_mc13892(void);
+extern struct cpu_wp *(*get_cpu_wp)(int *wp);
+extern void (*set_num_cpu_wp)(int num);
+static int num_cpu_wp = 3;
+
+/* working point(wp): 0 - 800MHz; 1 - 166.25MHz; */
+static struct cpu_wp cpu_wp_auto[] = {
+	{
+	 .pll_rate = 1000000000,
+	 .cpu_rate = 1000000000,
+	 .pdf = 0,
+	 .mfi = 10,
+	 .mfd = 11,
+	 .mfn = 5,
+	 .cpu_podf = 0,
+	 .cpu_voltage = 1175000,},
+	{
+	 .pll_rate = 800000000,
+	 .cpu_rate = 800000000,
+	 .pdf = 0,
+	 .mfi = 8,
+	 .mfd = 2,
+	 .mfn = 1,
+	 .cpu_podf = 0,
+	 .cpu_voltage = 1100000,},
+	{
+	 .pll_rate = 800000000,
+	 .cpu_rate = 166250000,
+	 .pdf = 4,
+	 .mfi = 8,
+	 .mfd = 2,
+	 .mfn = 1,
+	 .cpu_podf = 4,
+	 .cpu_voltage = 850000,},
+};
+
+struct cpu_wp *mx51_get_cpu_wp(int *wp)
+{
+	*wp = num_cpu_wp;
+	return cpu_wp_auto;
+}
+
+void mx51_set_num_cpu_wp(int num)
+{
+	num_cpu_wp = num;
+	return;
+}
+
+#if defined(CONFIG_MTD_NAND_MXC) \
+	|| defined(CONFIG_MTD_NAND_MXC_MODULE) \
+	|| defined(CONFIG_MTD_NAND_MXC_V2) \
+	|| defined(CONFIG_MTD_NAND_MXC_V2_MODULE) \
+	|| defined(CONFIG_MTD_NAND_MXC_V3) \
+	|| defined(CONFIG_MTD_NAND_MXC_V3_MODULE)
+
+extern void gpio_nand_active(void);
+extern void gpio_nand_inactive(void);
+
+static int nand_init(void)
+{
+       /* Configure the pins */
+      gpio_nand_active();
+      return 0;
+}
+
+static void nand_exit(void)
+{
+      /* Free the pins */
+      gpio_nand_inactive();
+}
+
+static struct flash_platform_data mxc_nand_data = {
+	.width = 1,
+	.init = nand_init,
+	.exit = nand_exit,
+};
+#endif
+
+#if defined(CONFIG_SMSC9118) || defined(CONFIG_SMSC9118_MODULE)
+static struct smc911x_platdata ccwmx51_smsc9118 = {
+	.flags          = 0,
+	.irq_flags      = IRQF_DISABLED | IRQF_TRIGGER_FALLING,
+	.irq_polarity   = 0,
+	.irq_type	= 1,	/* push-pull irq */
+};
+#endif
+
+#if defined(CONFIG_MMC_IMX_ESDHCI) || defined(CONFIG_MMC_IMX_ESDHCI_MODULE)
+static int sdhc_write_protect(struct device *dev)
+{
+     unsigned short rc = 0;
+
+     if (to_platform_device(dev)->id == 0)
+             rc = 0; /* Not supported WP on JSK board, therefore write is enabled */
+     else if (to_platform_device(dev)->id == 2)
+             rc = gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS1));
+     return rc;
+}
+
+static unsigned int sdhc_get_card_det_status(struct device *dev)
+{
+     int ret = 0;
+
+     if (to_platform_device(dev)->id == 0)
+    	 ret = gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_0));
+     else if (to_platform_device(dev)->id == 2)
+         ret = gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_GPIO_NAND));
+     return ret;
+}
+
+static struct mxc_mmc_platform_data mmc1_data = {
+	.ocr_mask = MMC_VDD_31_32,
+	.caps = MMC_CAP_4_BIT_DATA,
+	.min_clk = 400000,
+	.max_clk = 52000000,
+	.card_inserted_state = 1,
+	.status = sdhc_get_card_det_status,
+	.wp_status = sdhc_write_protect,
+	.clock_mmc = "esdhc_clk",
+	.power_mmc = NULL,
+};
+
+static struct mxc_mmc_platform_data mmc3_data = {
+	.ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 |
+	    MMC_VDD_31_32,
+	.caps = MMC_CAP_4_BIT_DATA,
+	.min_clk = 150000,
+	.max_clk = 50000000,
+	.card_inserted_state = 0,
+	.status = sdhc_get_card_det_status,
+	.wp_status = sdhc_write_protect,
+	.clock_mmc = "esdhc_clk",
+	.power_mmc = NULL,
+};
+#endif
+
+#if defined(CONFIG_FB_MXC_SYNC_PANEL) || defined(CONFIG_FB_MXC_SYNC_PANEL_MODULE)
+static struct resource mxcfb_resources[] = {
+	[0] = {
+	       .flags = IORESOURCE_MEM,
+	       },
+};
+#endif
+
+/*!
+ * Board specific fixup function. It is called by \b setup_arch() in
+ * setup.c file very early on during kernel starts. It allows the user to
+ * statically fill in the proper values for the passed-in parameters. None of
+ * the parameters is used currently.
+ *
+ * @param  desc         pointer to \b struct \b machine_desc
+ * @param  tags         pointer to \b struct \b tag
+ * @param  cmdline      pointer to the command line
+ * @param  mi           pointer to \b struct \b meminfo
+ */
+static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags,
+				   char **cmdline, struct meminfo *mi)
+{
+	char *str;
+	struct tag *t;
+	struct tag *mem_tag = 0;
+	int total_mem = SZ_512M;
+	int left_mem = 0;
+	int gpu_mem = SZ_64M;
+	int fb_mem = SZ_32M;
+
+	mxc_set_cpu_type(MXC_CPU_MX51);
+
+	get_cpu_wp = mx51_get_cpu_wp;
+	set_num_cpu_wp = mx51_set_num_cpu_wp;
+
+	for_each_tag(mem_tag, tags) {
+		if (mem_tag->hdr.tag == ATAG_MEM) {
+			total_mem = mem_tag->u.mem.size;
+			left_mem = total_mem - gpu_mem - fb_mem;
+			break;
+		}
+	}
+
+	for_each_tag(t, tags) {
+		if (t->hdr.tag == ATAG_CMDLINE) {
+			str = t->u.cmdline.cmdline;
+			str = strstr(str, "mem=");
+			if (str != NULL) {
+				str += 4;
+				left_mem = memparse(str, &str);
+				if (left_mem == 0 || left_mem > total_mem)
+					left_mem = total_mem - gpu_mem - fb_mem;
+			}
+
+			str = t->u.cmdline.cmdline;
+			str = strstr(str, "gpu_memory=");
+			if (str != NULL) {
+				str += 11;
+				gpu_mem = memparse(str, &str);
+			}
+
+			break;
+		}
+	}
+
+	if (mem_tag) {
+		fb_mem = total_mem - left_mem - gpu_mem;
+		if (fb_mem < 0) {
+			gpu_mem = total_mem - left_mem;
+			fb_mem = 0;
+		}
+		mem_tag->u.mem.size = left_mem;
+
+		/*reserve memory for gpu*/
+		gpu_device.resource[5].start =
+				mem_tag->u.mem.start + left_mem;
+		gpu_device.resource[5].end =
+				gpu_device.resource[5].start + gpu_mem - 1;
+#if defined(CONFIG_FB_MXC_SYNC_PANEL) || \
+	defined(CONFIG_FB_MXC_SYNC_PANEL_MODULE)
+		if (fb_mem) {
+			mxcfb_resources[0].start =
+				gpu_device.resource[5].end + 1;
+			mxcfb_resources[0].end =
+				mxcfb_resources[0].start + fb_mem - 1;
+		} else {
+			mxcfb_resources[0].start = 0;
+			mxcfb_resources[0].end = 0;
+		}
+#endif
+	}
+}
+
+#define PWGT1SPIEN (1<<15)
+#define PWGT2SPIEN (1<<16)
+#define USEROFFSPI (1<<3)
+
+static void mxc_power_off(void)
+{
+	/* We can do power down one of two ways:
+	   Set the power gating
+	   Set USEROFFSPI */
+
+	/* Set the power gate bits to power down */
+#ifdef CONFIG_MXC_PMIC_MC13892
+	pmic_write_reg(REG_POWER_MISC, (PWGT1SPIEN|PWGT2SPIEN),
+		(PWGT1SPIEN|PWGT2SPIEN));
+#endif
+}
+
+static struct i2c_board_info ccwmx51_i2c_devices[] __initdata = {
+#if defined(CONFIG_INPUT_MMA7455L) || defined(CONFIG_INPUT_MMA7455L_MODULE)
+	{
+        I2C_BOARD_INFO("mma7455l", 0x1d),
+		.irq = IOMUX_TO_IRQ(MX51_PIN_GPIO1_7),
+	},
+#endif
+#if defined(CONFIG_SND_SOC_IMX_CCWMX51_WM8753) || defined(CONFIG_SND_SOC_IMX_CCWMX51_WM8753_MODULE)
+	{
+        I2C_BOARD_INFO("wm8753", 0x1A),
+	},
+#endif
+};
+
+int __init ccwmx51_init_i2c2(void)
+{
+	return i2c_register_board_info(1, ccwmx51_i2c_devices , ARRAY_SIZE(ccwmx51_i2c_devices) );
+}
+
+static struct mxc_i2c_platform_data mxci2c_data = {
+	.i2c_clk = 100000,
+};
+
+static struct mxc_i2c_platform_data mxci2c_hs_data = {
+	.i2c_clk = 400000,
+};
+
+#if defined(CONFIG_SPI_MXC_SELECT1_SS1) && (defined(CONFIG_SPI_MXC) || defined(CONFIG_SPI_MXC_MODULE))
+static struct spi_board_info spi_devices[] __initdata = {
+#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
+	{	/* SPIDEV */
+		.modalias       = "spidev",
+		.max_speed_hz   = 6000000,
+		.bus_num        = 1,
+		.chip_select    = 1,
+	},
+	/* Add here other SPI devices, if any... */
+#endif
+};
+
+static void ccwmx51_init_spidevices(void)
+{
+	spi_register_board_info(spi_devices, ARRAY_SIZE(spi_devices));
+}
+#else
+static void ccwmx51_init_spidevices(void) { }
+#endif
+
+extern void ccwmx51_gpio_spi_chipselect_active(int cspi_mode, int status,
+						    int chipselect);
+extern void ccwmx51_gpio_spi_chipselect_inactive(int cspi_mode, int status,
+						      int chipselect);
+
+static struct mxc_spi_master mxcspi1_data = {
+	.maxchipselect = 4,
+	.spi_version = 23,
+	.chipselect_active = ccwmx51_gpio_spi_chipselect_active,
+	.chipselect_inactive = ccwmx51_gpio_spi_chipselect_inactive,
+};
+
+static struct mxc_srtc_platform_data srtc_data = {
+	.srtc_sec_mode_addr = 0x83F98840,
+};
+
+
+
+static struct mxc_ipu_config mxc_ipu_data = {
+	.rev = 2,
+};
+
+#if defined(CONFIG_W1_MASTER_MXC) || defined(CONFIG_W1_MASTER_MXC_MODULE)
+static struct mxc_w1_config mxc_w1_data = {
+	.search_rom_accelerator = 1,
+};
+#endif
+
+static struct mxc_spdif_platform_data mxc_spdif_data = {
+	.spdif_tx = 1,
+	.spdif_rx = 0,
+	.spdif_clk_44100 = 0,	/* spdif_ext_clk source for 44.1KHz */
+	.spdif_clk_48000 = 7,	/* audio osc source */
+	.spdif_clkid = 0,
+	.spdif_clk = NULL,	/* spdif bus clk */
+};
+
+static struct tve_platform_data tve_data = {
+	.dac_reg = "VVIDEO",
+	.dig_reg = "VDIG",
+};
+
+static struct mxc_dvfs_platform_data dvfs_core_data = {
+	.reg_id = "SW1",
+	.clk1_id = "cpu_clk",
+	.clk2_id = "gpc_dvfs_clk",
+	.gpc_cntr_reg_addr = MXC_GPC_CNTR,
+	.gpc_vcr_reg_addr = MXC_GPC_VCR,
+	.ccm_cdcr_reg_addr = MXC_CCM_CDCR,
+	.ccm_cacrr_reg_addr = MXC_CCM_CACRR,
+	.ccm_cdhipr_reg_addr = MXC_CCM_CDHIPR,
+	.dvfs_thrs_reg_addr = MXC_DVFSTHRS,
+	.dvfs_coun_reg_addr = MXC_DVFSCOUN,
+	.dvfs_emac_reg_addr = MXC_DVFSEMAC,
+	.dvfs_cntr_reg_addr = MXC_DVFSCNTR,
+	.prediv_mask = 0x1F800,
+	.prediv_offset = 11,
+	.prediv_val = 3,
+	.div3ck_mask = 0xE0000000,
+	.div3ck_offset = 29,
+	.div3ck_val = 2,
+	.emac_val = 0x08,
+	.upthr_val = 25,
+	.dnthr_val = 9,
+	.pncthr_val = 33,
+	.upcnt_val = 10,
+	.dncnt_val = 10,
+	.delay_time = 30,
+	.num_wp = 3,
+};
+
+static struct mxc_dvfsper_data dvfs_per_data = {
+	.reg_id = "SW2",
+	.clk_id = "gpc_dvfs_clk",
+	.gpc_cntr_reg_addr = MXC_GPC_CNTR,
+	.gpc_vcr_reg_addr = MXC_GPC_VCR,
+	.gpc_adu = 0x0,
+	.vai_mask = MXC_DVFSPMCR0_FSVAI_MASK,
+	.vai_offset = MXC_DVFSPMCR0_FSVAI_OFFSET,
+	.dvfs_enable_bit = MXC_DVFSPMCR0_DVFEN,
+	.irq_mask = MXC_DVFSPMCR0_FSVAIM,
+	.div3_offset = 0,
+	.div3_mask = 0x7,
+	.div3_div = 2,
+	.lp_high = 1200000,
+	.lp_low = 1200000,
+};
+
+static struct platform_pwm_backlight_data mxc_pwm_backlight_data = {
+	.pwm_id = 0,
+	.max_brightness = 255,
+	.dft_brightness = 128,
+	.pwm_period_ns = 78770,
+};
+
+static struct mxc_audio_platform_data wm8753_data = {
+    .ssi_num = 1,
+    .src_port = 2,
+    .ext_port = 3,
+    .sysclk = 12000000,
+};
+
+struct mxc_fb_platform_data mx51_fb_data[] = {
+	/*VGA*/
+	{
+			.interface_pix_fmt = IPU_PIX_FMT_RGB24,
+			.mode_str = "1024x768M-16@60",	/* Default */
+	}
+};
+#if defined(CONFIG_UIO_PDRV_GENIRQ) || defined(CONFIG_UIO_PDRV_GENIRQ_MODULE)
+static struct uio_info gpu2d_platform_data = {
+	.name = "imx_gpu2d",
+	.version = "1",
+	.irq = MXC_INT_GPU2_IRQ,
+	.open = gpu2d_open,
+	.release = gpu2d_release,
+	.mmap = gpu2d_mmap,
+};
+#endif
+
+#if defined(CONFIG_FB_MXC_SYNC_PANEL) || defined(CONFIG_FB_MXC_SYNC_PANEL_MODULE)
+struct ccwmx51_lcd_pdata * plcd_platform_data;
+
+struct ccwmx51_lcd_pdata * ccwmx51_get_display(char *name)
+{
+#if defined(CONFIG_CCWMX51_LQ070Y3DG3B) || defined(CONFIG_CCWMX51_CUSTOM)
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(lcd_display_list); i++)
+		if (!strncmp(lcd_display_list[i].fb_pdata.mode->name,
+			     name, strlen(lcd_display_list[i].fb_pdata.mode->name)))
+			return &lcd_display_list[i];
+#endif
+	return NULL;
+}
+
+static int __init ccwmx51_init_fb(void)
+{
+	char *options = NULL, *p;
+
+	if (fb_get_options("displayfb", &options))
+		pr_warning("no display information available in command line\n");
+
+	if (!options)
+		return -ENODEV;
+
+	if (!strncasecmp(options, "VGA", 3)) {
+		pr_info("VGA interface is primary\n");
+
+		/* Get the desired configuration provided by the bootloader */
+		if (options[3] != '@') {
+			pr_info("Video resolution for VGA interface not provided, using default\n");
+			/* TODO set default video here */
+		} else {
+			options = &options[4];
+			if (((p = strsep (&options, "@")) != NULL) && *p) {
+				if (!strcmp(p, "640x480x16")) {
+					strcpy(mx51_fb_data[0].mode_str, "640x480M-16@60");
+				} else if (!strcmp(p, "800x600x16")) {
+					strcpy(mx51_fb_data[0].mode_str, "800x600M-16@60");
+				} else if (!strcmp(p, "1024x768x16")) {
+					strcpy(mx51_fb_data[0].mode_str, "1024x768M-16@60");
+				} else if (!strcmp(p, "1280x1024x16")) {
+					strcpy(mx51_fb_data[0].mode_str, "1280x1024M-16@60");
+				} else
+					pr_warning("Unsuported video resolution: %s, using default\n", p);
+			}
+		}
+	} else {
+		if ((plcd_platform_data = ccwmx51_get_display(options)) != NULL) {
+			memcpy(&mx51_fb_data[0], &plcd_platform_data->fb_pdata, sizeof(struct mxc_fb_platform_data));
+			plcd_platform_data->vif = 0;	/* Select video interface 0 */
+		}
+	}
+	return 0;
+}
+device_initcall(ccwmx51_init_fb);
+#endif
+
+/*!
+ * Board specific initialization.
+ */
+static void __init mxc_board_init(void)
+{
+
+	mxc_ipu_data.di_clk[0] = clk_get(NULL, "ipu_di0_clk");
+	mxc_ipu_data.di_clk[1] = clk_get(NULL, "ipu_di1_clk");
+
+	mxc_spdif_data.spdif_core_clk = clk_get(NULL, "spdif_xtal_clk");
+	clk_put(mxc_spdif_data.spdif_core_clk);
+
+	mxc_cpu_common_init();
+	mxc_register_gpios();
+	ccwmx51_io_init();
+
+	mxc_register_device(&mxc_wdt_device, NULL);
+	mxc_register_device(&mxcspi1_device, &mxcspi1_data);
+	mxc_register_device(&mxci2c_devices[0], &mxci2c_data);
+	mxc_register_device(&mxci2c_devices[1], &mxci2c_data);
+	mxc_register_device(&mxci2c_hs_device, &mxci2c_hs_data);
+	mxc_register_device(&mxc_rtc_device, &srtc_data);
+	mxc_register_device(&mxc_ssi1_device, NULL);
+	mxc_register_device(&mxc_ssi2_device, NULL);
+	mxc_register_device(&mxc_dma_device, NULL);
+#if defined(CONFIG_W1_MASTER_MXC) || defined(CONFIG_W1_MASTER_MXC_MODULE)
+	mxc_register_device(&mxc_w1_master_device, &mxc_w1_data);
+#endif
+	mxc_ipu_data.di_clk[0] = clk_get(NULL, "ipu_di0_clk");
+	mxc_ipu_data.di_clk[1] = clk_get(NULL, "ipu_di1_clk");
+	mxc_register_device(&mxc_ipu_device, &mxc_ipu_data);
+	mxc_register_device(&mxcvpu_device, NULL);
+	mxc_register_device(&mxc_alsa_spdif_device, &mxc_spdif_data);
+	mxc_register_device(&mxc_tve_device, &tve_data);
+	mxc_register_device(&mx51_lpmode_device, NULL);
+	mxc_register_device(&busfreq_device, NULL);
+	mxc_register_device(&sdram_autogating_device, NULL);
+	mxc_register_device(&mxc_dvfs_core_device, &dvfs_core_data);
+	mxc_register_device(&mxc_dvfs_per_device, &dvfs_per_data);
+	mxc_register_device(&mxc_iim_device, NULL);
+	mxc_register_device(&gpu_device, NULL);
+#if defined(CONFIG_UIO_PDRV_GENIRQ) || defined(CONFIG_UIO_PDRV_GENIRQ_MODULE)
+	mxc_register_device(&mxc_gpu2d_device, &gpu2d_platform_data);
+#endif
+	mxc_register_device(&mxc_pwm1_device, NULL);
+	mxc_register_device(&mxc_pwm_backlight_device, &mxc_pwm_backlight_data);
+
+#if defined(CONFIG_MMC_IMX_ESDHCI) || defined(CONFIG_MMC_IMX_ESDHCI_MODULE)
+	/* SD card detect irqs */
+	mxcsdhc1_device.resource[2].start = IOMUX_TO_IRQ(MX51_PIN_GPIO1_0);
+	mxcsdhc1_device.resource[2].end = IOMUX_TO_IRQ(MX51_PIN_GPIO1_0);
+	mxcsdhc3_device.resource[2].start = IOMUX_TO_IRQ(MX51_PIN_GPIO_NAND);
+	mxcsdhc3_device.resource[2].end = IOMUX_TO_IRQ(MX51_PIN_GPIO_NAND);
+	mxc_register_device(&mxcsdhc1_device, &mmc1_data);
+	mxc_register_device(&mxcsdhc3_device, &mmc3_data);
+#endif
+#if defined(CONFIG_FEC) || defined(CONFIG_FEC_MODULE)
+	mxc_register_device(&mxc_fec_device, NULL);
+#endif
+#if defined(CONFIG_MTD_NAND_MXC) \
+	|| defined(CONFIG_MTD_NAND_MXC_MODULE) \
+	|| defined(CONFIG_MTD_NAND_MXC_V2) \
+	|| defined(CONFIG_MTD_NAND_MXC_V2_MODULE) \
+	|| defined(CONFIG_MTD_NAND_MXC_V3) \
+	|| defined(CONFIG_MTD_NAND_MXC_V3_MODULE)
+	mxc_register_device(&mxc_nandv2_mtd_device, &mxc_nand_data);
+#endif
+#if defined(CONFIG_SMSC9118) || defined(CONFIG_SMSC9118_MODULE)
+	mxc_register_device(&smsc911x_device, &ccwmx51_smsc9118);
+#endif
+#if defined(CONFIG_SND_SOC_IMX_CCWMX51_WM8753) || defined(CONFIG_SND_SOC_IMX_CCWMX51_WM8753_MODULE)
+	mxc_register_device(&mxc_wm8753_device, &wm8753_data);
+#endif
+	ccwmx51_init_spidevices();
+	ccwmx51_init_i2c2();
+#if defined(CONFIG_FB_MXC_SYNC_PANEL) || defined(CONFIG_FB_MXC_SYNC_PANEL_MODULE)
+	mxc_register_device(&lcd_pdev, plcd_platform_data);
+	mxc_fb_devices[0].num_resources = ARRAY_SIZE(mxcfb_resources);
+	mxc_fb_devices[0].resource = mxcfb_resources;
+	mxc_register_device(&mxc_fb_devices[0], &mx51_fb_data[0]);
+//	mxc_register_device(&mxc_fb_devices[1], &mx51_fb_data[1]);
+//	mxc_register_device(&mxc_fb_devices[2], NULL);
+#endif
+
+#ifdef CONFIG_MXC_PMIC_MC13892
+	ccwmx51_init_mc13892();
+	/* Configure PMIC irq line */
+	set_irq_type(IOMUX_TO_GPIO(MX51_PIN_GPIO1_5), IRQ_TYPE_EDGE_BOTH);
+#endif
+
+	pm_power_off = mxc_power_off;
+}
+
+static void __init ccwmx51_timer_init(void)
+{
+	struct clk *uart_clk;
+
+	/* Change the CPU voltages for TO2*/
+	if (cpu_is_mx51_rev(CHIP_REV_2_0) <= 1) {
+		cpu_wp_auto[0].cpu_voltage = 1175000;
+		cpu_wp_auto[1].cpu_voltage = 1100000;
+		cpu_wp_auto[2].cpu_voltage = 1000000;
+	}
+
+	mx51_clocks_init(32768, 24000000, 22579200, 24576000);
+
+	uart_clk = clk_get(NULL, "uart_clk.1");
+	early_console_setup(UART2_BASE_ADDR, uart_clk);
+}
+
+static struct sys_timer mxc_timer = {
+	.init	= ccwmx51_timer_init,
+};
+
+MACHINE_START(CCWMX51JS, "ConnectCore Wi-i.MX51 on a JSK board")
+	/* Maintainer: Digi International, Inc. */
+	.phys_io = AIPS1_BASE_ADDR,
+	.io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+	.boot_params = PHYS_OFFSET + 0x100,
+	.fixup = fixup_mxc_board,
+	.map_io = mx5_map_io,
+	.init_irq = mx5_init_irq,
+	.init_machine = mxc_board_init,
+	.timer = &mxc_timer,
+MACHINE_END
diff --git a/arch/arm/mach-mx5/mx51_ccwmx51js_gpio.c b/arch/arm/mach-mx5/mx51_ccwmx51js_gpio.c
new file mode 100644
index 000000000000..7922347f4f3e
--- /dev/null
+++ b/arch/arm/mach-mx5/mx51_ccwmx51js_gpio.c
@@ -0,0 +1,821 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2009-2010 Digi International, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/errno.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <mach/hardware.h>
+#include <mach/gpio.h>
+
+#include "iomux.h"
+#include "mx51_pins.h"
+
+static void ccwmx51_mmc2_gpio_active(void);
+
+
+/**
+ * iomux settings for the external ethernet mac
+ */
+#if defined(CONFIG_SMSC9118) || defined(CONFIG_SMSC9118_MODULE)
+static struct mxc_iomux_pin_cfg __initdata ccwmx51_iomux_ext_eth_pins[] = {
+	{MX51_PIN_EIM_CS5, IOMUX_CONFIG_ALT0,
+			(PAD_CTL_HYS_ENABLE | PAD_CTL_PUE_KEEPER | PAD_CTL_DRV_MEDIUM), },
+	{MX51_PIN_EIM_OE, IOMUX_CONFIG_ALT0,},
+	{MX51_PIN_EIM_DA0, IOMUX_CONFIG_ALT0,},
+	{MX51_PIN_EIM_DA1, IOMUX_CONFIG_ALT0,},
+	{MX51_PIN_EIM_DA2, IOMUX_CONFIG_ALT0,},
+	{MX51_PIN_EIM_DA3, IOMUX_CONFIG_ALT0,},
+	{MX51_PIN_EIM_DA4, IOMUX_CONFIG_ALT0,},
+	{MX51_PIN_EIM_DA5, IOMUX_CONFIG_ALT0,},
+	{MX51_PIN_EIM_DA6, IOMUX_CONFIG_ALT0,},
+	{MX51_PIN_EIM_DA7, IOMUX_CONFIG_ALT0,},
+	{MX51_PIN_EIM_D16, IOMUX_CONFIG_ALT0,},
+	{MX51_PIN_EIM_D17, IOMUX_CONFIG_ALT0,},
+	{MX51_PIN_EIM_D18, IOMUX_CONFIG_ALT0,},
+	{MX51_PIN_EIM_D19, IOMUX_CONFIG_ALT0,},
+	{MX51_PIN_EIM_D20, IOMUX_CONFIG_ALT0,},
+	{MX51_PIN_EIM_D21, IOMUX_CONFIG_ALT0,},
+	{MX51_PIN_EIM_D22, IOMUX_CONFIG_ALT0,},
+	{MX51_PIN_EIM_D23, IOMUX_CONFIG_ALT0,},
+	{MX51_PIN_EIM_D24, IOMUX_CONFIG_ALT0,},
+	{MX51_PIN_EIM_D25, IOMUX_CONFIG_ALT0,},
+	{MX51_PIN_EIM_D26, IOMUX_CONFIG_ALT0,},
+	{MX51_PIN_EIM_D27, IOMUX_CONFIG_ALT0,},
+	{MX51_PIN_EIM_D28, IOMUX_CONFIG_ALT0,},
+	{MX51_PIN_EIM_D29, IOMUX_CONFIG_ALT0,},
+	{MX51_PIN_EIM_D30, IOMUX_CONFIG_ALT0,},
+	{MX51_PIN_EIM_D31, IOMUX_CONFIG_ALT0,},
+	{MX51_PIN_GPIO1_9, IOMUX_CONFIG_ALT0, (PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU), },
+};
+#endif
+
+#if defined(CONFIG_MMC_IMX_ESDHCI) || defined(CONFIG_MMC_IMX_ESDHCI_MODULE)
+static struct mxc_iomux_pin_cfg __initdata ccwmx51_iomux_mmc_pins[] = {
+	/* SDHC1*/
+	{
+		MX51_PIN_SD1_CMD, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION,
+		(PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | PAD_CTL_DRV_HIGH |
+		PAD_CTL_47K_PU | PAD_CTL_SRE_FAST),
+	},
+	{
+		MX51_PIN_SD1_CLK, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION,
+		(PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | PAD_CTL_DRV_HIGH |
+		PAD_CTL_47K_PU | PAD_CTL_SRE_FAST),
+	},
+	{
+		MX51_PIN_SD1_DATA0, IOMUX_CONFIG_ALT0,
+		(PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | PAD_CTL_DRV_HIGH |
+		PAD_CTL_47K_PU | PAD_CTL_SRE_FAST),
+	},
+	{
+		MX51_PIN_SD1_DATA1, IOMUX_CONFIG_ALT0,
+		(PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | PAD_CTL_DRV_HIGH |
+		PAD_CTL_47K_PU | PAD_CTL_SRE_FAST),
+	},
+	{
+		MX51_PIN_SD1_DATA2, IOMUX_CONFIG_ALT0,
+		(PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | PAD_CTL_DRV_HIGH |
+		PAD_CTL_47K_PU | PAD_CTL_SRE_FAST),
+	},
+	{
+		MX51_PIN_SD1_DATA3, IOMUX_CONFIG_ALT0,
+		(PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | PAD_CTL_DRV_HIGH |
+		PAD_CTL_47K_PU | PAD_CTL_SRE_FAST),
+	},
+	{
+		MX51_PIN_GPIO1_0, IOMUX_CONFIG_GPIO | IOMUX_CONFIG_SION,
+		(PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU),
+	},
+
+	/* SDHC3*/
+	{
+		MX51_PIN_NANDF_RDY_INT, IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION,
+		(PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST),
+	},
+	{
+		MX51_PIN_NANDF_CS7, IOMUX_CONFIG_ALT5,
+		(PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST),
+	},
+	{	/* SD3 DATA0 */
+		MX51_PIN_NANDF_D8, IOMUX_CONFIG_ALT5,
+		(PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST),
+		MUX_IN_ESDHC3_IPP_DAT0_IN_SELECT_INPUT, INPUT_CTL_PATH1
+	},
+	{	/* SD3 DATA1 */
+		MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT5,
+		(PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST),
+		MUX_IN_ESDHC3_IPP_DAT1_IN_SELECT_INPUT, INPUT_CTL_PATH1
+	},
+	{	/* SD3 DATA2 */
+		MX51_PIN_NANDF_D10, IOMUX_CONFIG_ALT5,
+		(PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST),
+		MUX_IN_ESDHC3_IPP_DAT2_IN_SELECT_INPUT, INPUT_CTL_PATH1
+	},
+	{	/* SD3 DATA3 */
+		MX51_PIN_NANDF_D11, IOMUX_CONFIG_ALT5,
+		(PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST),
+		MUX_IN_ESDHC3_IPP_DAT3_IN_SELECT_INPUT, INPUT_CTL_PATH1
+	},
+	{	/* SD3 Card detect */
+		MX51_PIN_GPIO_NAND, IOMUX_CONFIG_GPIO | IOMUX_CONFIG_SION,
+		(PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU),
+	},
+	{	/* SD3 Write protect */
+		MX51_PIN_NANDF_CS1, IOMUX_CONFIG_GPIO | IOMUX_CONFIG_SION,
+		(PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU),
+	},
+};
+#endif
+
+#if defined(CONFIG_USB_EHCI_ARC_H1) || defined(CONFIG_USB_EHCI_ARC_H1_MODULE)
+static struct mxc_iomux_pin_cfg __initdata ccwmx51_iomux_usbh1_pins[] = {
+	{	/* USBH1_STP */
+		MX51_PIN_USBH1_STP, IOMUX_CONFIG_ALT0,
+		(PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_KEEPER |
+		PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE),
+	},
+	{	/* USBH1_CLK */
+		MX51_PIN_USBH1_CLK, IOMUX_CONFIG_ALT0,
+		(PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_KEEPER |
+		PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_DDR_INPUT_CMOS),
+	},
+	{	/* USBH1_DIR */
+		MX51_PIN_USBH1_DIR, IOMUX_CONFIG_ALT0,
+		(PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_KEEPER |
+		PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_DDR_INPUT_CMOS),
+	},
+	{	/* USBH1_NXT */
+		MX51_PIN_USBH1_NXT, IOMUX_CONFIG_ALT0,
+		(PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | PAD_CTL_PUE_KEEPER |
+		PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_DDR_INPUT_CMOS),
+	},
+	{	/* USBH1_DATA0 */
+		MX51_PIN_USBH1_DATA0, IOMUX_CONFIG_ALT0,
+		(PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
+		PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE),
+	},
+	{	/* USBH1_DATA1 */
+		MX51_PIN_USBH1_DATA1, IOMUX_CONFIG_ALT0,
+		(PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
+		PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE),
+	},
+	{	/* USBH1_DATA2 */
+		MX51_PIN_USBH1_DATA2, IOMUX_CONFIG_ALT0,
+		(PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
+		PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE),
+	},
+	{	/* USBH1_DATA3 */
+		MX51_PIN_USBH1_DATA3, IOMUX_CONFIG_ALT0,
+		(PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
+		PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE),
+	},
+	{	/* USBH1_DATA4 */
+		MX51_PIN_USBH1_DATA4, IOMUX_CONFIG_ALT0,
+		(PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
+		PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE),
+	},
+	{	/* USBH1_DATA5 */
+		MX51_PIN_USBH1_DATA5, IOMUX_CONFIG_ALT0,
+		(PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
+		PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE),
+	},
+	{	/* USBH1_DATA6 */
+		MX51_PIN_USBH1_DATA6, IOMUX_CONFIG_ALT0,
+		(PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
+		PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE),
+	},
+	{	/* USBH1_DATA7 */
+		MX51_PIN_USBH1_DATA7, IOMUX_CONFIG_ALT0,
+		(PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
+		PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE),
+	},
+	{	/* USBH PHY RESET */
+		MX51_PIN_DISPB2_SER_RS, IOMUX_CONFIG_GPIO,
+		(PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU |
+		PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE),
+	},
+};
+#endif
+
+#if defined(CONFIG_FB_MXC_SYNC_PANEL) || defined(CONFIG_FB_MXC_SYNC_PANEL_MODULE)
+static struct mxc_iomux_pin_cfg __initdata ccwmx51_iomux_video1_pins[] = {
+	{	/* DISP1 DAT0 */
+		MX51_PIN_DISP1_DAT0, IOMUX_CONFIG_ALT0,
+		(PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST),
+	},
+	{	/* DISP1 DAT1 */
+		MX51_PIN_DISP1_DAT1, IOMUX_CONFIG_ALT0,
+		(PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST),
+	},
+	{	/* DISP1 DAT2 */
+		MX51_PIN_DISP1_DAT2, IOMUX_CONFIG_ALT0,
+		(PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST),
+	},
+	{	/* DISP1 DAT3 */
+		MX51_PIN_DISP1_DAT3, IOMUX_CONFIG_ALT0,
+		(PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST),
+	},
+	{	/* DISP1 DAT4 */
+		MX51_PIN_DISP1_DAT4, IOMUX_CONFIG_ALT0,
+		(PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST),
+	},
+	{	/* DISP1 DAT5 */
+		MX51_PIN_DISP1_DAT5, IOMUX_CONFIG_ALT0,
+		(PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST),
+	},
+	{	/* DISP1 DAT6 */
+		MX51_PIN_DISP1_DAT6, IOMUX_CONFIG_ALT0,
+		(PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST),
+	},
+	{	/* DISP1 DAT7 */
+		MX51_PIN_DISP1_DAT7, IOMUX_CONFIG_ALT0,
+		(PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST),
+	},
+	{	/* DISP1 DAT8 */
+		MX51_PIN_DISP1_DAT8, IOMUX_CONFIG_ALT0,
+		(PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST),
+	},
+	{	/* DISP1 DAT9 */
+		MX51_PIN_DISP1_DAT9, IOMUX_CONFIG_ALT0,
+		(PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST),
+	},
+	{	/* DISP1 DAT10 */
+		MX51_PIN_DISP1_DAT10, IOMUX_CONFIG_ALT0,
+		(PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST),
+	},
+	{	/* DISP1 DAT11 */
+		MX51_PIN_DISP1_DAT11, IOMUX_CONFIG_ALT0,
+		(PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST),
+	},
+	{	/* DISP1 DAT12 */
+		MX51_PIN_DISP1_DAT12, IOMUX_CONFIG_ALT0,
+		(PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST),
+	},
+	{	/* DISP1 DAT13 */
+		MX51_PIN_DISP1_DAT13, IOMUX_CONFIG_ALT0,
+		(PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST),
+	},
+	{	/* DISP1 DAT14 */
+		MX51_PIN_DISP1_DAT14, IOMUX_CONFIG_ALT0,
+		(PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST),
+	},
+	{	/* DISP1 DAT15 */
+		MX51_PIN_DISP1_DAT15, IOMUX_CONFIG_ALT0,
+		(PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST),
+	},
+	{	/* DISP1 DAT16 */
+		MX51_PIN_DISP1_DAT16, IOMUX_CONFIG_ALT0,
+		(PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST),
+	},
+	{	/* DISP1 DAT17 */
+		MX51_PIN_DISP1_DAT17, IOMUX_CONFIG_ALT0,
+		(PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST),
+	},
+	{	/* DISP1 DAT18 */
+		MX51_PIN_DISP1_DAT18, IOMUX_CONFIG_ALT0,
+		(PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST),
+	},
+	{	/* DISP1 DAT19 */
+		MX51_PIN_DISP1_DAT19, IOMUX_CONFIG_ALT0,
+		(PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST),
+	},
+	{	/* DISP1 DAT20 */
+		MX51_PIN_DISP1_DAT20, IOMUX_CONFIG_ALT0,
+		(PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST),
+	},
+	{	/* DISP1 DAT21 */
+		MX51_PIN_DISP1_DAT21, IOMUX_CONFIG_ALT0,
+		(PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST),
+	},
+	{	/* DISP1 DAT22 */
+		MX51_PIN_DISP1_DAT22, IOMUX_CONFIG_ALT0,
+		(PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST),
+	},
+	{	/* DISP1 DAT23 */
+		MX51_PIN_DISP1_DAT23, IOMUX_CONFIG_ALT0,
+		(PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST),
+	},
+	{	/*  LCD1 Power Enable, as gpio */
+		MX51_PIN_DI1_PIN11, IOMUX_CONFIG_GPIO,
+		(PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU |
+		PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE),
+	},
+};
+#endif
+
+#if defined(CONFIG_I2C_MXC) || defined(CONFIG_I2C_MXC_MODULE)
+static struct mxc_iomux_pin_cfg __initdata ccwmx51_iomux_i2c_pins[] = {
+#ifdef CONFIG_I2C_MXC_SELECT1
+	{
+		MX51_PIN_SD2_CMD, IOMUX_CONFIG_ALT1 | IOMUX_CONFIG_SION,
+		(PAD_CTL_SRE_FAST | PAD_CTL_ODE_OPENDRAIN_ENABLE | PAD_CTL_HYS_ENABLE |
+		PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH),
+		MUX_IN_I2C1_IPP_SDA_IN_SELECT_INPUT, INPUT_CTL_PATH2,
+	},
+	{
+		MX51_PIN_SD2_CLK, IOMUX_CONFIG_ALT1 | IOMUX_CONFIG_SION,
+		(PAD_CTL_SRE_FAST | PAD_CTL_ODE_OPENDRAIN_ENABLE | PAD_CTL_HYS_ENABLE |
+		PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH),
+		MUX_IN_I2C1_IPP_SCL_IN_SELECT_INPUT, INPUT_CTL_PATH2,
+	},
+#endif
+#ifdef CONFIG_I2C_MXC_SELECT2
+	{
+		MX51_PIN_GPIO1_2, IOMUX_CONFIG_ALT2 | IOMUX_CONFIG_SION,
+		(PAD_CTL_SRE_FAST | PAD_CTL_ODE_OPENDRAIN_ENABLE | PAD_CTL_DRV_HIGH |
+		PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE),
+		MUX_IN_I2C2_IPP_SCL_IN_SELECT_INPUT, INPUT_CTL_PATH3,
+	},
+	{
+		MX51_PIN_GPIO1_3, IOMUX_CONFIG_ALT2 | IOMUX_CONFIG_SION,
+		(PAD_CTL_SRE_FAST | PAD_CTL_ODE_OPENDRAIN_ENABLE | PAD_CTL_DRV_HIGH |
+		PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE),
+		MUX_IN_I2C2_IPP_SDA_IN_SELECT_INPUT, INPUT_CTL_PATH3,
+	},
+#endif
+#ifdef CONFIG_I2C_MXC_SELECT3
+	{
+		MX51_PIN_I2C1_CLK, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION,
+		(PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_HYS_ENABLE |
+		PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | PAD_CTL_SRE_SLOW),
+	},
+	{
+		MX51_PIN_I2C1_DAT, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION,
+		(PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_HYS_ENABLE |
+		PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | PAD_CTL_SRE_SLOW),
+	}
+#endif
+};
+#endif /* defined(CONFIG_I2C_MXC) || defined(CONFIG_I2C_MXC_MODULE) */
+
+static struct mxc_iomux_pin_cfg __initdata ccwmx51_iomux_devices_pins[] = {
+	{	/* PMIC interrupt line */
+		MX51_PIN_GPIO1_5, IOMUX_CONFIG_GPIO | IOMUX_CONFIG_SION,
+		(PAD_CTL_SRE_SLOW | PAD_CTL_DRV_MEDIUM | PAD_CTL_100K_PU |
+		PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_VOT_HIGH),
+	},
+#if defined(CONFIG_INPUT_MMA7455L) || defined(CONFIG_INPUT_MMA7455L_MODULE)
+	{	/* MMA7455L interrupt line */
+		MX51_PIN_GPIO1_6, IOMUX_CONFIG_GPIO,
+	},
+	{
+		MX51_PIN_GPIO1_7, IOMUX_CONFIG_ALT2,
+		(PAD_CTL_DRV_HIGH | PAD_CTL_PUE_PULL |
+		PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST),
+	},
+#endif
+};
+
+#if defined(CONFIG_SND_SOC_WM8753) || defined(CONFIG_SND_SOC_WM8753_MODULE)
+static struct mxc_iomux_pin_cfg __initdata ccwmx51_audio_pins[] = {
+
+	/* TODO: the SSI interface should be selectable through configuration */
+	{	/* AUD3_BB_CK */
+		MX51_PIN_AUD3_BB_CK, IOMUX_CONFIG_ALT0 ,
+		(PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
+		PAD_CTL_HYS_NONE | PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_PKE_ENABLE |
+		PAD_CTL_PUE_KEEPER ),
+	},
+	{	/* AUD3_BB_FS */
+		MX51_PIN_AUD3_BB_FS, IOMUX_CONFIG_ALT0 ,
+		(PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | PAD_CTL_HYS_NONE |
+		PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE),
+	},
+	{	/* AUD3_BB_RXD */
+		MX51_PIN_AUD3_BB_RXD, IOMUX_CONFIG_ALT0 ,
+		(PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | PAD_CTL_HYS_NONE |
+		PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE),
+	},
+	{	/* AUD3_BB_TXD */
+		MX51_PIN_AUD3_BB_TXD, IOMUX_CONFIG_ALT0 ,
+		(PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
+		PAD_CTL_HYS_NONE | PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_PKE_ENABLE |
+		PAD_CTL_PUE_KEEPER ),
+	},
+};
+#endif
+
+#if defined(CONFIG_SPI_MXC) || defined(CONFIG_SPI_MXC_MODULE)
+static struct mxc_iomux_pin_cfg __initdata ccwmx51_cspi_pins[] = {
+#ifdef CONFIG_SPI_MXC_SELECT1
+	/* ECSPI1 */
+	{	/* MISO */
+		MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0,
+		(PAD_CTL_HYS_NONE | PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_PUE_KEEPER | PAD_CTL_DRV_HIGH |
+		PAD_CTL_SRE_FAST),
+	},
+	{	/* MOSI */
+		MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0,
+		(PAD_CTL_HYS_NONE | PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_PUE_KEEPER | PAD_CTL_DRV_HIGH |
+		PAD_CTL_SRE_FAST),
+	},
+	{	/* SCLK */
+		MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0,
+		(PAD_CTL_HYS_NONE | PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_PUE_KEEPER | PAD_CTL_DRV_HIGH |
+		PAD_CTL_SRE_FAST),
+	},
+	{	/* SS0 */
+		MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_GPIO,
+		(PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU |
+		PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE),
+	},
+#ifdef CONFIG_SPI_MXC_SELECT1_SS1
+	{	/* SS1 */
+		MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_GPIO,
+		(PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU |
+		PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE),
+	},
+#endif
+#endif
+#ifdef CONFIG_SPI_MXC_SELECT2
+	/* ECSPI2 */
+	{	/* SCLK */
+		MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT2,
+		(PAD_CTL_SRE_SLOW | PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_DRV_LOW |
+		PAD_CTL_PUE_KEEPER | PAD_CTL_HYS_ENABLE),
+	},
+	{	/* MISO */
+		MX51_PIN_NANDF_RB3, IOMUX_CONFIG_ALT2,
+		(PAD_CTL_SRE_SLOW | PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_DRV_HIGH |
+		PAD_CTL_PUE_KEEPER | PAD_CTL_HYS_ENABLE),
+	},
+	{	/* MOSI */
+		MX51_PIN_NANDF_D15, IOMUX_CONFIG_ALT2,
+		(PAD_CTL_SRE_SLOW | PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_DRV_HIGH |
+		PAD_CTL_PUE_KEEPER | PAD_CTL_HYS_ENABLE),
+	},
+	{	/* SS0 */
+		MX51_PIN_NANDF_RDY_INT, IOMUX_CONFIG_ALT2,
+		(PAD_CTL_SRE_SLOW | PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_DRV_LOW |
+		PAD_CTL_PUE_KEEPER | PAD_CTL_HYS_ENABLE),
+	},
+	{	/* SI_VER_TO2, SS1 */
+		MX51_PIN_NANDF_D12, IOMUX_CONFIG_ALT2,
+		(PAD_CTL_SRE_SLOW | PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_DRV_HIGH |
+		PAD_CTL_PUE_KEEPER | PAD_CTL_HYS_ENABLE),
+	},
+	{	/* SI_VER_TO2, RDY */
+		MX51_PIN_NANDF_RB1, IOMUX_CONFIG_ALT2,
+		(PAD_CTL_SRE_SLOW | PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_DRV_LOW |
+		PAD_CTL_PUE_KEEPER | PAD_CTL_HYS_ENABLE),
+	},
+#endif
+#ifdef CONFIG_SPI_MXC_SELECT3
+	/* ECSPI3 */
+	{
+		MX51_PIN_USBH1_CLK, IOMUX_CONFIG_ALT2,
+		(PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
+		 PAD_CTL_DRV_MEDIUM | PAD_CTL_HYS_ENABLE | PAD_CTL_SRE_SLOW),
+	},
+	{
+		MX51_PIN_USBH1_DATA4, IOMUX_CONFIG_ALT2,
+		(PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_HYS_ENABLE | PAD_CTL_PUE_KEEPER |
+		PAD_CTL_DRV_MEDIUM | PAD_CTL_HYS_ENABLE | PAD_CTL_SRE_SLOW),
+	},
+	{
+		MX51_PIN_USBH1_DATA5, IOMUX_CONFIG_ALT2,
+		(PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_HYS_ENABLE | PAD_CTL_PUE_KEEPER |
+		PAD_CTL_DRV_MEDIUM | PAD_CTL_HYS_ENABLE | PAD_CTL_SRE_SLOW),
+	},
+	{
+		MX51_PIN_USBH1_NXT, IOMUX_CONFIG_ALT2,
+		(PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_HYS_ENABLE | PAD_CTL_PUE_KEEPER |
+		PAD_CTL_DRV_MEDIUM | PAD_CTL_HYS_ENABLE | PAD_CTL_SRE_SLOW),
+	},
+	{
+		MX51_PIN_USBH1_DIR, IOMUX_CONFIG_ALT2,
+		(PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
+		PAD_CTL_DRV_MEDIUM | PAD_CTL_HYS_ENABLE | PAD_CTL_SRE_SLOW),
+	},
+	{
+		MX51_PIN_USBH1_STP, IOMUX_CONFIG_ALT2,
+		(PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_HYS_ENABLE | PAD_CTL_PUE_KEEPER |
+		PAD_CTL_DRV_MEDIUM | PAD_CTL_HYS_ENABLE | PAD_CTL_SRE_SLOW),
+	},
+#endif
+};
+
+/* workaround for ecspi chipselect pin may not keep correct level when idle */
+void ccwmx51_gpio_spi_chipselect_active(int busnum, int ssb_pol, int chipselect)
+{
+	u8 mask = 0x1 << (chipselect - 1);
+
+	switch (busnum) {
+	case 1:
+		switch (chipselect) {
+		case 0x1:
+			gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS0),
+				       (ssb_pol & mask) ?  1 : 0);
+			break;
+		case 0x2:
+			gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS1),
+				       (ssb_pol & mask) ?  1 : 0);
+			break;
+		default:
+			break;
+		}
+		break;
+	case 2:
+	case 3:
+	default:
+		break;
+	}
+}
+EXPORT_SYMBOL(ccwmx51_gpio_spi_chipselect_active);
+
+void ccwmx51_gpio_spi_chipselect_inactive(int busnum, int ssb_pol,
+					  int chipselect)
+{
+	u8 mask = 0x1 << (chipselect - 1);
+
+	switch (busnum) {
+	case 1:
+		switch (chipselect) {
+		case 0x1:
+			gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS0),
+				       (ssb_pol & mask) ?  0 : 1);
+			break;
+		case 0x2:
+			gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS1),
+				       (ssb_pol & mask) ?  0 : 1);
+			break;
+		default:
+			break;
+		}
+		break;
+	case 2:
+	case 3:
+	default:
+		break;
+	}
+}
+EXPORT_SYMBOL(ccwmx51_gpio_spi_chipselect_inactive);
+
+#endif /* defined(CONFIG_SPI_MXC) || defined(CONFIG_SPI_MXC_MODULE) */
+
+void __init ccwmx51_io_init(void)
+{
+	int i;
+
+#if defined(CONFIG_SMSC9118) || defined(CONFIG_SMSC9118_MODULE)
+	for (i = 0; i < ARRAY_SIZE(ccwmx51_iomux_ext_eth_pins); i++) {
+		mxc_request_iomux(ccwmx51_iomux_ext_eth_pins[i].pin,
+				ccwmx51_iomux_ext_eth_pins[i].mux_mode);
+		if (ccwmx51_iomux_ext_eth_pins[i].pad_cfg)
+			mxc_iomux_set_pad(ccwmx51_iomux_ext_eth_pins[i].pin,
+					ccwmx51_iomux_ext_eth_pins[i].pad_cfg);
+		if (ccwmx51_iomux_ext_eth_pins[i].in_select)
+			mxc_iomux_set_input(ccwmx51_iomux_ext_eth_pins[i].in_select,
+					ccwmx51_iomux_ext_eth_pins[i].in_mode);
+	}
+#endif
+
+#if defined(CONFIG_MMC_IMX_ESDHCI) || defined(CONFIG_MMC_IMX_ESDHCI_MODULE)
+	for (i = 0; i < ARRAY_SIZE(ccwmx51_iomux_mmc_pins); i++) {
+		mxc_request_iomux(ccwmx51_iomux_mmc_pins[i].pin,
+				  ccwmx51_iomux_mmc_pins[i].mux_mode);
+		if (ccwmx51_iomux_mmc_pins[i].pad_cfg)
+			mxc_iomux_set_pad(ccwmx51_iomux_mmc_pins[i].pin,
+					  ccwmx51_iomux_mmc_pins[i].pad_cfg);
+		if (ccwmx51_iomux_mmc_pins[i].in_select)
+			mxc_iomux_set_input(ccwmx51_iomux_mmc_pins[i].in_select,
+					    ccwmx51_iomux_mmc_pins[i].in_mode);
+	}
+#endif
+
+#if defined(CONFIG_USB_EHCI_ARC_H1) || defined(CONFIG_USB_EHCI_ARC_H1_MODULE)
+	for (i = 0; i < ARRAY_SIZE(ccwmx51_iomux_usbh1_pins); i++) {
+		mxc_request_iomux(ccwmx51_iomux_usbh1_pins[i].pin,
+				  ccwmx51_iomux_usbh1_pins[i].mux_mode);
+		if (ccwmx51_iomux_usbh1_pins[i].pad_cfg)
+			mxc_iomux_set_pad(ccwmx51_iomux_usbh1_pins[i].pin,
+					  ccwmx51_iomux_usbh1_pins[i].pad_cfg);
+		if (ccwmx51_iomux_usbh1_pins[i].in_select)
+			mxc_iomux_set_input(ccwmx51_iomux_usbh1_pins[i].in_select,
+					    ccwmx51_iomux_usbh1_pins[i].in_mode);
+	}
+#endif
+
+#if defined(CONFIG_FB_MXC_SYNC_PANEL) || defined(CONFIG_FB_MXC_SYNC_PANEL_MODULE)
+	for (i = 0; i < ARRAY_SIZE(ccwmx51_iomux_video1_pins); i++) {
+		mxc_request_iomux(ccwmx51_iomux_video1_pins[i].pin,
+				  ccwmx51_iomux_video1_pins[i].mux_mode);
+		if (ccwmx51_iomux_video1_pins[i].pad_cfg)
+			mxc_iomux_set_pad(ccwmx51_iomux_video1_pins[i].pin,
+					  ccwmx51_iomux_video1_pins[i].pad_cfg);
+		if (ccwmx51_iomux_video1_pins[i].in_select)
+			mxc_iomux_set_input(ccwmx51_iomux_video1_pins[i].in_select,
+					    ccwmx51_iomux_video1_pins[i].in_mode);
+	}
+	/*  LCD Power Enable */
+	gpio_request(IOMUX_TO_GPIO(MX51_PIN_DI1_PIN11), "gpio3_0");
+	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_DI1_PIN11), 0);
+#endif
+
+#if defined(CONFIG_I2C_MXC) || defined(CONFIG_I2C_MXC_MODULE)
+	for (i = 0; i < ARRAY_SIZE(ccwmx51_iomux_i2c_pins); i++) {
+		mxc_request_iomux(ccwmx51_iomux_i2c_pins[i].pin,
+				ccwmx51_iomux_i2c_pins[i].mux_mode);
+		if (ccwmx51_iomux_i2c_pins[i].pad_cfg)
+			mxc_iomux_set_pad(ccwmx51_iomux_i2c_pins[i].pin,
+					ccwmx51_iomux_i2c_pins[i].pad_cfg);
+		if (ccwmx51_iomux_i2c_pins[i].in_select)
+			mxc_iomux_set_input(ccwmx51_iomux_i2c_pins[i].in_select,
+					ccwmx51_iomux_i2c_pins[i].in_mode);
+	}
+#endif
+
+#if defined(CONFIG_SND_SOC_WM8753) || defined(CONFIG_SND_SOC_WM8753_MODULE)
+	for (i = 0; i < ARRAY_SIZE(ccwmx51_audio_pins); i++) {
+		mxc_request_iomux(ccwmx51_audio_pins[i].pin,
+				  ccwmx51_audio_pins[i].mux_mode);
+		if (ccwmx51_audio_pins[i].pad_cfg)
+			mxc_iomux_set_pad(ccwmx51_audio_pins[i].pin,
+					  ccwmx51_audio_pins[i].pad_cfg);
+		if (ccwmx51_audio_pins[i].in_select)
+			mxc_iomux_set_input(ccwmx51_audio_pins[i].in_select,
+					    ccwmx51_audio_pins[i].in_mode);
+	}
+#endif
+
+#if defined(CONFIG_SPI_MXC) || defined(CONFIG_SPI_MXC_MODULE)
+	for (i = 0; i < ARRAY_SIZE(ccwmx51_cspi_pins); i++) {
+		mxc_request_iomux(ccwmx51_cspi_pins[i].pin,
+				  ccwmx51_cspi_pins[i].mux_mode);
+		if (ccwmx51_cspi_pins[i].pad_cfg)
+			mxc_iomux_set_pad(ccwmx51_cspi_pins[i].pin,
+					  ccwmx51_cspi_pins[i].pad_cfg);
+		if (ccwmx51_cspi_pins[i].in_select)
+			mxc_iomux_set_input(ccwmx51_cspi_pins[i].in_select,
+					    ccwmx51_cspi_pins[i].in_mode);
+	}
+#ifdef CONFIG_SPI_MXC_SELECT1
+	gpio_request(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS0), "cspi1_ss0");
+	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS0), 0);
+	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS0), 0);
+#ifdef CONFIG_SPI_MXC_SELECT1_SS1
+	gpio_request(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS1), "cspi1_ss1");
+	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS1), 0);
+	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS1), 0);
+#endif
+#endif
+
+#endif
+
+	for (i = 0; i < ARRAY_SIZE(ccwmx51_iomux_devices_pins); i++) {
+		mxc_request_iomux(ccwmx51_iomux_devices_pins[i].pin,
+				  ccwmx51_iomux_devices_pins[i].mux_mode);
+		if (ccwmx51_iomux_devices_pins[i].pad_cfg)
+			mxc_iomux_set_pad(ccwmx51_iomux_devices_pins[i].pin,
+					  ccwmx51_iomux_devices_pins[i].pad_cfg);
+		if (ccwmx51_iomux_devices_pins[i].in_select)
+			mxc_iomux_set_input(ccwmx51_iomux_devices_pins[i].in_select,
+					    ccwmx51_iomux_devices_pins[i].in_mode);
+	}
+
+	/* PMIC interrupt line */
+	gpio_request(IOMUX_TO_GPIO(MX51_PIN_GPIO1_5), "gpio1_5");
+	gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_5));
+
+#if defined(CONFIG_USB_EHCI_ARC_H1) || defined(CONFIG_USB_EHCI_ARC_H1_MODULE)
+	/* USB PHY/HUB reset*/
+	gpio_request(IOMUX_TO_GPIO(MX51_PIN_DISPB2_SER_RS), "gpio3_8");
+	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_DISPB2_SER_RS), 0);
+	msleep(1);
+	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_DISPB2_SER_RS), 1);
+#endif
+
+#if defined(CONFIG_MMC_IMX_ESDHCI) || defined(CONFIG_MMC_IMX_ESDHCI_MODULE)
+	/* For the wireless module */
+	ccwmx51_mmc2_gpio_active();
+#endif
+}
+
+#if defined(CONFIG_MMC_IMX_ESDHCI) || defined(CONFIG_MMC_IMX_ESDHCI_MODULE)
+/* IOMUX settings, for the wireless interface */
+static struct mxc_iomux_pin_cfg __initdata ccwmx51_iomux_mmc2_pins[] = {
+	/* SDHC2*/
+	{
+		MX51_PIN_SD2_CMD, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION,
+		(PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | PAD_CTL_DRV_HIGH |
+		PAD_CTL_47K_PU | PAD_CTL_SRE_FAST),
+	},
+	{
+		MX51_PIN_SD2_CLK, IOMUX_CONFIG_ALT0,
+		(PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | PAD_CTL_DRV_HIGH |
+		PAD_CTL_47K_PU | PAD_CTL_SRE_FAST),
+	},
+	{
+		MX51_PIN_SD2_DATA0, IOMUX_CONFIG_ALT0,
+		(PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | PAD_CTL_DRV_HIGH |
+		PAD_CTL_47K_PU | PAD_CTL_SRE_FAST),
+	},
+	{
+		MX51_PIN_SD2_DATA1, IOMUX_CONFIG_ALT0,
+		(PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | PAD_CTL_DRV_HIGH |
+		PAD_CTL_47K_PU | PAD_CTL_SRE_FAST),
+	},
+	{
+		MX51_PIN_SD2_DATA2, IOMUX_CONFIG_ALT0,
+		(PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | PAD_CTL_DRV_HIGH |
+		PAD_CTL_47K_PU | PAD_CTL_SRE_FAST),
+	},
+	{
+		MX51_PIN_SD2_DATA3, IOMUX_CONFIG_ALT0,
+		(PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | PAD_CTL_DRV_HIGH |
+		PAD_CTL_47K_PU | PAD_CTL_SRE_FAST),
+	},
+};
+
+static void ccwmx51_mmc2_gpio_active(void)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(ccwmx51_iomux_mmc2_pins); i++) {
+		mxc_request_iomux(ccwmx51_iomux_mmc2_pins[i].pin,
+				  ccwmx51_iomux_mmc2_pins[i].mux_mode);
+		if (ccwmx51_iomux_mmc2_pins[i].pad_cfg)
+			mxc_iomux_set_pad(ccwmx51_iomux_mmc2_pins[i].pin,
+					  ccwmx51_iomux_mmc2_pins[i].pad_cfg);
+		if (ccwmx51_iomux_mmc2_pins[i].in_select)
+			mxc_iomux_set_input(ccwmx51_iomux_mmc2_pins[i].in_select,
+					    ccwmx51_iomux_mmc2_pins[i].in_mode);
+	}
+}
+
+void ccwmx51_mmc2_gpio_inactive(void)
+{
+}
+#endif
+
+#if defined(CONFIG_SERIAL_MXC) || defined(CONFIG_SERIAL_MXC_MODULE)
+#define SERIAL_PORT_PAD		(PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | \
+				 PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH | \
+				 PAD_CTL_SRE_FAST)
+
+void gpio_uart_active(int port, int no_irda)
+{
+	/* Configure the IOMUX control registers for the UART signals */
+	switch (port) {
+
+	case 0:		/* UART 1 IOMUX Configs */
+#ifdef CONFIG_UART1_ENABLED
+		mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0);
+		mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0);
+		mxc_iomux_set_pad(MX51_PIN_UART1_RXD, SERIAL_PORT_PAD);
+		mxc_iomux_set_pad(MX51_PIN_UART1_TXD, SERIAL_PORT_PAD);
+		mxc_iomux_set_input(MUX_IN_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, INPUT_CTL_PATH0);
+
+		/* TODO enable CTS/RTS if selected */
+#endif
+		break;
+
+	case 1:		/* UART 2 IOMUX Configs */
+#ifdef CONFIG_UART2_ENABLED
+		mxc_request_iomux(MX51_PIN_UART2_RXD, IOMUX_CONFIG_ALT0);
+		mxc_request_iomux(MX51_PIN_UART2_TXD, IOMUX_CONFIG_ALT0);
+		mxc_iomux_set_pad(MX51_PIN_UART2_RXD, SERIAL_PORT_PAD);
+		mxc_iomux_set_pad(MX51_PIN_UART2_TXD, SERIAL_PORT_PAD);
+		mxc_iomux_set_input(MUX_IN_UART2_IPP_UART_RXD_MUX_SELECT_INPUT, INPUT_CTL_PATH2);
+
+		/*  TODO enable CTS/RTS if selected */
+#endif
+		break;
+	case 2:		/* UART 3 IOMUX Configs */
+#ifdef CONFIG_UART3_ENABLED
+		mxc_request_iomux(MX51_PIN_UART3_RXD, IOMUX_CONFIG_ALT1);
+		mxc_request_iomux(MX51_PIN_UART3_TXD, IOMUX_CONFIG_ALT1);
+		mxc_iomux_set_pad(MX51_PIN_UART3_RXD, SERIAL_PORT_PAD);
+		mxc_iomux_set_pad(MX51_PIN_UART3_TXD, SERIAL_PORT_PAD);
+		mxc_iomux_set_input(MUX_IN_UART3_IPP_UART_RXD_MUX_SELECT_INPUT, INPUT_CTL_PATH4);
+
+		/* TODO enable CTS/RTS if selected */
+#endif
+		break;
+	default:
+		break;
+	}
+
+}
+
+#else
+void gpio_uart_active(int port, int no_irda) {}
+#endif
+void gpio_uart_inactive(int port, int no_irda) {}
+EXPORT_SYMBOL(gpio_uart_active);
+EXPORT_SYMBOL(gpio_uart_inactive);
+
+
+
diff --git a/arch/arm/mach-mx5/mx51_ccwmx51js_pmic_mc13892.c b/arch/arm/mach-mx5/mx51_ccwmx51js_pmic_mc13892.c
new file mode 100644
index 000000000000..88864efe3b56
--- /dev/null
+++ b/arch/arm/mach-mx5/mx51_ccwmx51js_pmic_mc13892.c
@@ -0,0 +1,363 @@
+ /*
+ * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2009 Digi International, Inc. All Rights Reserved.
+  */
+
+ /*
+  * The code contained herein is licensed under the GNU General Public
+  * License. You may obtain a copy of the GNU General Public License
+  * Version 2 or later at the following locations:
+  *
+  * http://www.opensource.org/licenses/gpl-license.html
+  * http://www.gnu.org/copyleft/gpl.html
+  */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/spi/spi.h>
+#include <linux/err.h>
+#include <linux/pmic_external.h>
+#include <linux/regulator/machine.h>
+#include <linux/mfd/mc13892/core.h>
+#include "iomux.h"
+#include <mach/irqs.h>
+#include "mx51_pins.h"
+
+/*
+ * Convenience conversion.
+ * Here atm, maybe there is somewhere better for this.
+ */
+#define mV_to_uV(mV) (mV * 1000)
+#define uV_to_mV(uV) (uV / 1000)
+#define V_to_uV(V) (mV_to_uV(V * 1000))
+#define uV_to_V(uV) (uV_to_mV(uV) / 1000)
+
+/* Coin cell charger enable */
+#define CIONCHEN_LSH	23
+#define CIONCHEN_WID	1
+/* Coin cell charger voltage setting */
+#define VCOIN_LSH	20
+#define VCOIN_WID	3
+
+/* Coin Charger voltage */
+#define VCOIN_2_5V	0x0
+#define VCOIN_2_7V	0x1
+#define VCOIN_2_8V	0x2
+#define VCOIN_2_9V	0x3
+#define VCOIN_3_0V	0x4
+#define VCOIN_3_1V	0x5
+#define VCOIN_3_2V	0x6
+#define VCOIN_3_3V	0x7
+
+/* Keeps VSRTC and CLK32KMCU on for all states */
+#define DRM_LSH 4
+#define DRM_WID 1
+
+/* regulator standby mask */
+#define GEN1_STBY_MASK		(1 << 1)
+#define IOHI_STBY_MASK		(1 << 4)
+#define DIG_STBY_MASK		(1 << 10)
+#define GEN2_STBY_MASK		(1 << 13)
+#define PLL_STBY_MASK		(1 << 16)
+#define USB2_STBY_MASK		(1 << 19)
+
+#define GEN3_STBY_MASK		(1 << 1)
+#define CAM_STBY_MASK		(1 << 7)
+#define VIDEO_STBY_MASK		(1 << 13)
+#define AUDIO_STBY_MASK		(1 << 16)
+#define SD_STBY_MASK		(1 << 19)
+
+/* 0x92412 */
+#define REG_MODE_0_ALL_MASK	(GEN1_STBY_MASK |\
+				DIG_STBY_MASK | GEN2_STBY_MASK |\
+				PLL_STBY_MASK | USB2_STBY_MASK)
+/* 0x92082 */
+#define REG_MODE_1_ALL_MASK	(GEN3_STBY_MASK | CAM_STBY_MASK |\
+				VIDEO_STBY_MASK | AUDIO_STBY_MASK |\
+				SD_STBY_MASK)
+
+/* CPU */
+static struct regulator_consumer_supply sw1_consumers[] = {
+	{
+		.supply = "cpu_vcc",
+	}
+};
+
+struct mc13892;
+
+static struct regulator_init_data sw1_init = {
+	.constraints = {
+		.name = "SW1",
+		.min_uV = mV_to_uV(600),
+		.max_uV = mV_to_uV(1375),
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+		.valid_modes_mask = 0,
+		.always_on = 1,
+		.boot_on = 1,
+		.initial_state = PM_SUSPEND_MEM,
+		.state_mem = {
+			.uV = 850000,
+			.mode = REGULATOR_MODE_NORMAL,
+			.enabled = 1,
+		},
+	},
+	.num_consumer_supplies = ARRAY_SIZE(sw1_consumers),
+	.consumer_supplies = sw1_consumers,
+};
+
+static struct regulator_init_data sw2_init = {
+	.constraints = {
+		.name = "SW2",
+		.min_uV = mV_to_uV(900),
+		.max_uV = mV_to_uV(1850),
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+		.always_on = 1,
+		.boot_on = 1,
+		.initial_state = PM_SUSPEND_MEM,
+		.state_mem = {
+			.uV = 950000,
+			.mode = REGULATOR_MODE_NORMAL,
+			.enabled = 1,
+		},
+	}
+};
+
+static struct regulator_init_data sw3_init = {
+	.constraints = {
+		.name = "SW3",
+		.min_uV = mV_to_uV(1100),
+		.max_uV = mV_to_uV(1850),
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+		.always_on = 1,
+		.boot_on = 1,
+	}
+};
+
+static struct regulator_init_data sw4_init = {
+	.constraints = {
+		.name = "SW4",
+		.min_uV = mV_to_uV(1100),
+		.max_uV = mV_to_uV(1850),
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+		.always_on = 1,
+		.boot_on = 1,
+	}
+};
+
+static struct regulator_init_data viohi_init = {
+	.constraints = {
+		.name = "VIOHI",
+		.boot_on = 1,
+	}
+};
+
+static struct regulator_init_data vusb_init = {
+	.constraints = {
+		.name = "VUSB",
+		.boot_on = 1,
+	}
+};
+
+static struct regulator_init_data swbst_init = {
+	.constraints = {
+		.name = "SWBST",
+	}
+};
+
+static struct regulator_init_data vdig_init = {
+	.constraints = {
+		.name = "VDIG",
+		.min_uV = mV_to_uV(1050),
+		.max_uV = mV_to_uV(1800),
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+		.boot_on = 1,
+	}
+};
+
+static struct regulator_init_data vpll_init = {
+	.constraints = {
+		.name = "VPLL",
+		.min_uV = mV_to_uV(1050),
+		.max_uV = mV_to_uV(1800),
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+		.boot_on = 1,
+	}
+};
+
+static struct regulator_init_data vusb2_init = {
+	.constraints = {
+		.name = "VUSB2",
+		.min_uV = mV_to_uV(2400),
+		.max_uV = mV_to_uV(2775),
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+		.boot_on = 1,
+	}
+};
+
+static struct regulator_init_data vvideo_init = {
+	.constraints = {
+		.name = "VVIDEO",
+		.min_uV = mV_to_uV(2775),
+		.max_uV = mV_to_uV(2775),
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+		.always_on = 1,
+		.apply_uV =1,
+	}
+};
+
+static struct regulator_init_data vaudio_init = {
+	.constraints = {
+		.name = "VAUDIO",
+		.min_uV = mV_to_uV(2300),
+		.max_uV = mV_to_uV(3000),
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+	}
+};
+
+static struct regulator_init_data vsd_init = {
+	.constraints = {
+		.name = "VSD",
+		.min_uV = mV_to_uV(1800),
+		.max_uV = mV_to_uV(3150),
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+	}
+};
+
+static struct regulator_init_data vcam_init = {
+	.constraints = {
+		.name = "VCAM",
+		.min_uV = mV_to_uV(2500),
+		.max_uV = mV_to_uV(3000),
+		.valid_ops_mask =
+			REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_MODE,
+		.valid_modes_mask = REGULATOR_MODE_FAST | REGULATOR_MODE_NORMAL,
+	}
+};
+
+static struct regulator_init_data vgen1_init = {
+	.constraints = {
+		.name = "VGEN1",
+		.min_uV = mV_to_uV(1200),
+		.max_uV = mV_to_uV(3150),
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+	}
+};
+
+static struct regulator_init_data vgen2_init = {
+	.constraints = {
+		.name = "VGEN2",
+		.min_uV = mV_to_uV(1200),
+		.max_uV = mV_to_uV(3150),
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+	}
+};
+
+static struct regulator_init_data vgen3_init = {
+	.constraints = {
+		.name = "VGEN3",
+		.min_uV = mV_to_uV(1800),
+		.max_uV = mV_to_uV(2900),
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+	}
+};
+
+static struct regulator_init_data gpo1_init = {
+	.constraints = {
+		.name = "GPO1",
+	}
+};
+
+static struct regulator_init_data gpo2_init = {
+	.constraints = {
+		.name = "GPO2",
+	}
+};
+
+static struct regulator_init_data gpo3_init = {
+	.constraints = {
+		.name = "GPO3",
+	}
+};
+
+static struct regulator_init_data gpo4_init = {
+	.constraints = {
+		.name = "GPO4",
+	}
+};
+
+static int mc13892_regulator_init(struct mc13892 *mc13892)
+{
+	unsigned int value, register_mask;
+	printk("Initializing regulators for CCWMX51.\n");
+	if (mxc_cpu_is_rev(CHIP_REV_2_0) < 0)
+		sw2_init.constraints.state_mem.uV = 1100000;
+	else if (mxc_cpu_is_rev(CHIP_REV_2_0) == 1) {
+		sw2_init.constraints.state_mem.uV = 1250000;
+		sw1_init.constraints.state_mem.uV = 1000000;
+	}
+
+	/* enable standby controll for all regulators */
+	pmic_read_reg(REG_MODE_0, &value, 0xffffff);
+	value |= REG_MODE_0_ALL_MASK;
+	pmic_write_reg(REG_MODE_0, value, 0xffffff);
+
+	pmic_read_reg(REG_MODE_1, &value, 0xffffff);
+	value |= REG_MODE_1_ALL_MASK;
+	pmic_write_reg(REG_MODE_1, value, 0xffffff);
+
+	/* Enable coin cell charger */
+	value = BITFVAL(CIONCHEN, 1) | BITFVAL(VCOIN, VCOIN_3_0V);
+	register_mask = BITFMASK(CIONCHEN) | BITFMASK(VCOIN);
+	pmic_write_reg(REG_POWER_CTL0, value, register_mask);
+
+#if defined(CONFIG_RTC_DRV_MXC_V2) || defined(CONFIG_RTC_DRV_MXC_V2_MODULE)
+	value = BITFVAL(DRM, 1);
+	register_mask = BITFMASK(DRM);
+	pmic_write_reg(REG_POWER_CTL0, value, register_mask);
+#endif
+
+	mc13892_register_regulator(mc13892, MC13892_SW1, &sw1_init);
+	mc13892_register_regulator(mc13892, MC13892_SW2, &sw2_init);
+	mc13892_register_regulator(mc13892, MC13892_SW3, &sw3_init);
+	mc13892_register_regulator(mc13892, MC13892_SW4, &sw4_init);
+	mc13892_register_regulator(mc13892, MC13892_SWBST, &swbst_init);
+	mc13892_register_regulator(mc13892, MC13892_VIOHI, &viohi_init);
+	mc13892_register_regulator(mc13892, MC13892_VPLL, &vpll_init);
+	mc13892_register_regulator(mc13892, MC13892_VDIG, &vdig_init);
+	mc13892_register_regulator(mc13892, MC13892_VSD, &vsd_init);
+	mc13892_register_regulator(mc13892, MC13892_VUSB2, &vusb2_init);
+	mc13892_register_regulator(mc13892, MC13892_VVIDEO, &vvideo_init);
+	mc13892_register_regulator(mc13892, MC13892_VAUDIO, &vaudio_init);
+	mc13892_register_regulator(mc13892, MC13892_VCAM, &vcam_init);
+	mc13892_register_regulator(mc13892, MC13892_VGEN1, &vgen1_init);
+	mc13892_register_regulator(mc13892, MC13892_VGEN2, &vgen2_init);
+	mc13892_register_regulator(mc13892, MC13892_VGEN3, &vgen3_init);
+	mc13892_register_regulator(mc13892, MC13892_VUSB, &vusb_init);
+	mc13892_register_regulator(mc13892, MC13892_GPO1, &gpo1_init);
+	mc13892_register_regulator(mc13892, MC13892_GPO2, &gpo2_init);
+	mc13892_register_regulator(mc13892, MC13892_GPO3, &gpo3_init);
+	mc13892_register_regulator(mc13892, MC13892_GPO4, &gpo4_init);
+
+	return 0;
+}
+
+static struct mc13892_platform_data mc13892_plat = {
+	.init = mc13892_regulator_init,
+};
+
+static struct spi_board_info __initdata mc13892_spi_device = {
+	.modalias = "pmic_spi",
+	.irq = IOMUX_TO_IRQ(MX51_PIN_GPIO1_5),
+	.max_speed_hz = 6000000,	/* XXX: Increase this clock to 18MHz later */
+	.bus_num = 1,
+	.chip_select = 0,
+	.platform_data = &mc13892_plat,
+};
+
+
+int __init ccwmx51_init_mc13892(void)
+{
+	return spi_register_board_info(&mc13892_spi_device, 1);
+}
+
diff --git a/arch/arm/mach-mx5/usb_dr.c b/arch/arm/mach-mx5/usb_dr.c
index e72ec58cbf3a..658583b65ab6 100644
--- a/arch/arm/mach-mx5/usb_dr.c
+++ b/arch/arm/mach-mx5/usb_dr.c
@@ -20,6 +20,7 @@
 #include <mach/hardware.h>
 #include "usb.h"
 
+#if defined(CONFIG_USB_OTG) || defined(CONFIG_USB_EHCI_ARC_OTG) || defined(CONFIG_USB_GADGET_ARC)
 static int usbotg_init_ext(struct platform_device *pdev);
 static void usbotg_uninit_ext(struct fsl_usb2_platform_data *pdata);
 static void _wake_up_enable(struct fsl_usb2_platform_data *pdata, bool enable);
@@ -137,6 +138,7 @@ static void usbotg_clock_gate(bool on)
 		clk_put(usb_clk);
 	}
 }
+#endif
 
 void __init mx5_usb_dr_init(void)
 {