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authorRanjani Vaidyanathan <ra5478@freescale.com>2012-08-23 22:57:50 -0500
committerXinyu Chen <xinyu.chen@freescale.com>2012-08-24 13:37:17 +0800
commite61df589a843d28483c6d94a9d7c0b3517e6e832 (patch)
treebcf70d3916244e090dbca003b4f43db3c2403a24 /arch/arm/mach-mx6/clock.c
parentac8f43ae39627e6ddb2072521fc8b6014c48e7cd (diff)
ENGR00221277 MX6DL/S - Set AXI clock to 270MHzimx-android-r13.4-beta
Change AXI_CLK to be sourced from PLL3_PFD1_540MHz, so that it can run at 270MHz on MX6DL/S. This is required for improving VPU performance. Change AXI_CLK to be sourced from periph_clk just before the DDR freq is going to be dropped to 24MHz/50MHz. Change it back to PLL3_PFD1_540 when the DDR freq is back at 400MHz. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
Diffstat (limited to 'arch/arm/mach-mx6/clock.c')
-rw-r--r--arch/arm/mach-mx6/clock.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm/mach-mx6/clock.c b/arch/arm/mach-mx6/clock.c
index 7fa93d0bb5fd..93b60ac679e3 100644
--- a/arch/arm/mach-mx6/clock.c
+++ b/arch/arm/mach-mx6/clock.c
@@ -5398,14 +5398,15 @@ int __init mx6_clocks_init(unsigned long ckil, unsigned long osc,
/* pxp & epdc */
clk_set_parent(&ipu2_clk, &pll2_pfd_400M);
clk_set_rate(&ipu2_clk, 200000000);
+ clk_set_parent(&axi_clk, &pll3_pfd_540M);
} else if (cpu_is_mx6q()) {
clk_set_parent(&gpu3d_core_clk[0], &mmdc_ch0_axi_clk[0]);
clk_set_rate(&gpu3d_core_clk[0], 528000000);
clk_set_parent(&ipu2_clk, &mmdc_ch0_axi_clk[0]);
clk_set_parent(&ipu1_clk, &mmdc_ch0_axi_clk[0]);
+ clk_set_parent(&axi_clk, &periph_clk);
}
- clk_set_parent(&axi_clk, &periph_clk);
/* Need to keep PLL3_PFD_540M enabled until AXI is sourced from it. */
clk_enable(&axi_clk);