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authorWayne Zou <b36644@freescale.com>2012-07-05 13:14:46 +0800
committerTerry Lv <r65388@freescale.com>2012-07-25 13:10:51 +0800
commite3047fe1322247d1e188b5745df7aee470d2412a (patch)
tree10ed7700ac06d59d21585f791c9316c06d6be71e /arch/arm/mach-mx6/clock.c
parent7548a846af2889283a4943b2114a103b39fe9c40 (diff)
ENGR00216109 MX6Q/DL clock: VDOA needs OCRAM clock and DDR clock enabled
VDOA needs OCRAM clock and DDR clock enabled when video playback, and set bus clock high to finish work quickly. Signed-off-by: Wayne Zou <b36644@freescale.com>
Diffstat (limited to 'arch/arm/mach-mx6/clock.c')
-rw-r--r--arch/arm/mach-mx6/clock.c17
1 files changed, 14 insertions, 3 deletions
diff --git a/arch/arm/mach-mx6/clock.c b/arch/arm/mach-mx6/clock.c
index 2173838c3a2c..600cd8b23414 100644
--- a/arch/arm/mach-mx6/clock.c
+++ b/arch/arm/mach-mx6/clock.c
@@ -1989,15 +1989,26 @@ static struct clk vdo_axi_clk = {
.set_parent = _clk_vdo_axi_set_parent,
};
-static struct clk vdoa_clk = {
+static struct clk vdoa_clk[] = {
+ {
__INIT_CLK_DEBUG(vdoa_clk)
.id = 0,
.parent = &vdo_axi_clk,
- .secondary = &ipg_clk,
.enable_reg = MXC_CCM_CCGR2,
.enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
.enable = _clk_enable,
.disable = _clk_disable,
+ .secondary = &vdoa_clk[1],
+ .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
+ },
+ {
+ .parent = &mmdc_ch0_axi_clk[0],
+ .secondary = &vdoa_clk[2],
+ },
+ {
+ .parent = &mx6fast1_clk,
+ .secondary = &ocram_clk,
+ },
};
static unsigned long _clk_gpt_get_rate(struct clk *clk)
@@ -5245,7 +5256,7 @@ static struct clk_lookup lookups[] = {
_REGISTER_CLOCK(NULL, "hdmi_isfr_clk", hdmi_clk[0]),
_REGISTER_CLOCK(NULL, "hdmi_iahb_clk", hdmi_clk[1]),
_REGISTER_CLOCK(NULL, "mipi_pllref_clk", mipi_pllref_clk),
- _REGISTER_CLOCK(NULL, "vdoa", vdoa_clk),
+ _REGISTER_CLOCK(NULL, "vdoa", vdoa_clk[0]),
_REGISTER_CLOCK(NULL, NULL, aips_tz2_clk),
_REGISTER_CLOCK(NULL, NULL, aips_tz1_clk),
_REGISTER_CLOCK(NULL, "clko_clk", clko_clk),