diff options
| author | Ranjani Vaidyanathan <ra5478@freescale.com> | 2012-08-29 17:05:11 -0500 |
|---|---|---|
| committer | Eric Nelson <eric.nelson@boundarydevices.com> | 2012-10-12 07:11:59 -0700 |
| commit | 9ddda0cfb25767529990f723f7e8bbc3fc555dc6 (patch) | |
| tree | 8856e82d2744d37e6901c230cb8371632d5be744 /arch/arm/mach-mx6/clock.c | |
| parent | 7869089487e0ddf3a77f17394c40a4756aea2546 (diff) | |
ENGR00221975 Fix race condition in clock code.
Need to ensure that check for usecount in clk_set_parent
occurs within the protection of the clock mutex. Else
there is a chance that the usecount can be decremented
(and the clock disabled) after the check.
Also add back the code to maintain the correct usecount
for pll2_pfd_400.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
Diffstat (limited to 'arch/arm/mach-mx6/clock.c')
| -rw-r--r-- | arch/arm/mach-mx6/clock.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/mach-mx6/clock.c b/arch/arm/mach-mx6/clock.c index 81b63a55c529..c2bf20177909 100644 --- a/arch/arm/mach-mx6/clock.c +++ b/arch/arm/mach-mx6/clock.c @@ -1262,6 +1262,7 @@ static int _clk_arm_set_rate(struct clk *clk, unsigned long rate) */ if (pll1_sw_clk.parent != &pll2_pfd_400M) { pll2_pfd_400M.enable(&pll2_pfd_400M); + pll2_pfd_400M.usecount++; arm_needs_pll2_400 = true; pll1_sw_clk.set_parent(&pll1_sw_clk, &pll2_pfd_400M); pll1_sw_clk.parent = &pll2_pfd_400M; @@ -1287,6 +1288,8 @@ static int _clk_arm_set_rate(struct clk *clk, unsigned long rate) /* Make sure pll1_sw_clk is from pll1_sys_main_clk */ pll1_sw_clk.set_parent(&pll1_sw_clk, &pll1_sys_main_clk); pll1_sw_clk.parent = &pll1_sys_main_clk; + if (arm_needs_pll2_400) + pll2_pfd_400M.usecount--; arm_needs_pll2_400 = false; if (pll2_pfd_400M.usecount == 0) pll2_pfd_400M.disable(&pll2_pfd_400M); |