ENGR00218747 - MX6Q/MX6DL: WAIT mode support for MX6QTO1.2/MX6DLTO1.1

Add the new WAIT mode workaround added for MX6Q1.2 and MX6DLTO1.1.
A new bit is added to CCM_CGPR (bit 17). This bit needs to be
enabled for the WAIT mode fix to be active and needs to be disabled
before the system enters STOP mode with power gating enabled.
Fix WAIT mode bug when system is in low power IDLE mode:
In low power IDLE mode (AHB @ 24MHz), switch ARM to run from 24MHz
on MX6QTO1.1 and MX6DLTO1.0 chips when ARM core enters WAIT mode.
We still need to use the ARM:IPG_CLK ratio of 12:5. Since IPG_CLK
is at 12MHz, we need to run ARM below 28.8MHz.

Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>

1 files changed, 0 insertions, 19 deletions

diff --git a/arch/arm/mach-mx6/clock.c b/arch/arm/mach-mx6/clock.c
index 0f87ce4d4ae1..34c26d4d3bc0 100644
--- a/arch/arm/mach-mx6/clock.c
+++ b/arch/arm/mach-mx6/clock.c
@@ -50,8 +50,6 @@ extern int lp_med_freq;
 extern int wait_mode_arm_podf;
 extern int lp_audio_freq;
 extern int cur_arm_podf;
-extern bool arm_mem_clked_in_wait;
-extern bool enable_wait_mode;
 
 void __iomem *apll_base;
 
@@ -1295,23 +1293,6 @@ static int _clk_arm_set_rate(struct clk *clk, unsigned long rate)
 	ipg_clk_rate = clk_get_rate(&ipg_clk);
 	max_arm_wait_clk = (12 * ipg_clk_rate) / 5;
 	wait_mode_arm_podf = parent_rate / max_arm_wait_clk;
-	if (wait_mode_arm_podf > 7) {
-		/* IPG_CLK is too low and we cannot get a ARM_CLK
-		  * that will satisfy the 12:5 ratio.
-		  * Use the mem_ipg_stop_mask bit to ensure clocks to ARM
-		  * memories are not gated during WAIT mode.
-		  * This bit is NOT available on MX6DQ TO1.1/TO1.0 and
-		  * MX6DL TO1.0.
-		  * Else disable entry to WAIT mode.
-		  */
-		if ((mx6q_revision() > IMX_CHIP_REVISION_1_1) ||
-			(mx6dl_revision() > IMX_CHIP_REVISION_1_0))
-			arm_mem_clked_in_wait = true;
-		else {
-			enable_wait_mode = false;
-			pr_info("wait mode is disabled due to ipg clock is too low\n");
-		}
-	}
 
 	if (div == 0)
 		div = 1;