diff options
| author | Fugang Duan <B38611@freescale.com> | 2013-07-11 18:59:20 +0800 |
|---|---|---|
| committer | Fugang Duan <B38611@freescale.com> | 2013-07-15 14:43:09 +0800 |
| commit | 2efc39f50660cb36519206736f9c72a98824e490 (patch) | |
| tree | 911981e5e12871c16ce24e090a009b3e5638f10a /arch/arm/mach-mx6/clock_mx6sl.c | |
| parent | 9e268cc3e4386f1a5a31a62f7207e5a9b8420124 (diff) | |
ENGR00270697-1 MX6: correct fec MDC clock source
For imx6 serial silicon, fec MDC clock parent is ipg 66MHz.
The current clock file define the clock source is enet_pll8 50Mhz.
So, the MDC clock is more than 2.5Mhz after divider.
The phy Ar8031 work fine in current MDC clock, which shows the phy
have exceeding flexibility. Correct the parent clock source to make
MDC clock little than 2.5Mhz.
Signed-off-by: Fugang Duan <B38611@freescale.com>
Diffstat (limited to 'arch/arm/mach-mx6/clock_mx6sl.c')
| -rwxr-xr-x | arch/arm/mach-mx6/clock_mx6sl.c | 14 |
1 files changed, 13 insertions, 1 deletions
diff --git a/arch/arm/mach-mx6/clock_mx6sl.c b/arch/arm/mach-mx6/clock_mx6sl.c index d8f33877bfe0..f375b4ac9dd4 100755 --- a/arch/arm/mach-mx6/clock_mx6sl.c +++ b/arch/arm/mach-mx6/clock_mx6sl.c @@ -3195,6 +3195,17 @@ static struct clk fec_clk[] = { }, }; +static unsigned long _clk_fec_mdc_get_rate(struct clk *clk) +{ + return clk_get_rate(clk->parent); +} + +static struct clk fec_mdc_clk = { + __INIT_CLK_DEBUG(fec_mdc_clk) + .parent = &ipg_clk, + .get_rate = _clk_fec_mdc_get_rate, +}; + static struct clk ecspi_clk[] = { { __INIT_CLK_DEBUG(ecspi0_clk) @@ -3974,7 +3985,8 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK("mxc_pwm.1", NULL, pwm_clk[1]), _REGISTER_CLOCK("mxc_pwm.2", NULL, pwm_clk[2]), _REGISTER_CLOCK("mxc_pwm.3", NULL, pwm_clk[3]), - _REGISTER_CLOCK("fec.0", NULL, fec_clk[0]), + _REGISTER_CLOCK(NULL, "fec_clk", fec_clk[0]), + _REGISTER_CLOCK(NULL, "fec_mdc_clk", fec_mdc_clk), _REGISTER_CLOCK(NULL, "usboh3_clk", usboh3_clk[0]), _REGISTER_CLOCK(NULL, "usb_phy1_clk", usb_phy1_clk), _REGISTER_CLOCK(NULL, "usb_phy3_clk", usb_phy3_clk), |