ENGR00179574: MX6- Add bus frequency scaling support

Add support for scaling the bus frequency (both DDR
and ahb_clk).
The DDR and AHB_CLK are dropped to 24MHz when all devices
that need high AHB frequency are disabled and the CORE
frequency is at the lowest setpoint.
The DDR is dropped to 400MHz for the video playback usecase.
In this mode the GPU, FEC, SATA etc are disabled.

To scale the bus frequency, its necessary that all cores
except the core that is executing the DDR frequency change
are in WFE. This is achieved by generating interrupts on
un-used interrupts (Int no 139, 144, 145 and 146).

Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>

1 files changed, 6 insertions, 2 deletions

diff --git a/arch/arm/mach-mx6/cpu.c b/arch/arm/mach-mx6/cpu.c
index 840102698112..6f3765e23523 100644
--- a/arch/arm/mach-mx6/cpu.c
+++ b/arch/arm/mach-mx6/cpu.c
@@ -33,6 +33,11 @@
 
 extern unsigned int num_cpu_idle_lock;
 
+void *mx6_wait_in_iram_base;
+void (*mx6_wait_in_iram)(void);
+extern void mx6_wait(void);
+extern int init_mmdc_settings(void);
+
 struct cpu_op *(*get_cpu_op)(int *op);
 bool enable_wait_mode;
 u32 arm_max_freq = CPU_AT_1GHz;
@@ -87,8 +92,6 @@ static int __init post_cpu_init(void)
 {
 	unsigned int reg;
 	void __iomem *base;
-	unsigned long iram_paddr, cpaddr;
-
 
 	iram_init(MX6Q_IRAM_BASE_ADDR, MX6Q_IRAM_SIZE);
 
@@ -129,6 +132,7 @@ static int __init post_cpu_init(void)
 
 	num_cpu_idle_lock = 0x0;
 
+	init_mmdc_settings();
 	return 0;
 }
 postcore_initcall(post_cpu_init);