diff options
| author | Danny Nold <dannynold@freescale.com> | 2012-01-19 14:53:51 -0600 |
|---|---|---|
| committer | Nitin Garg <nitin.garg@freescale.com> | 2014-06-03 21:48:17 -0500 |
| commit | 18861a55870dea70f0e411e7df9bda9b61199752 (patch) | |
| tree | 5c1c01a99d5dd5f8f033d8ddf59998aeb1e18f00 /arch/arm/mach-mx6/crm_regs.h | |
| parent | 04c0d8e5bf6b610640ded5b5dd3752ef18754521 (diff) | |
ENGR00172360-1 - MXC HDMI: New TO1.1 PLL5/PLL4 dividers not set up in clock co
Update get_rate, set_rate, and round_rate for audio_video PLLs
to account for new dividers added for MX6Q TO1.1. Since default value
for one of these dividers is 4, this is important for function of clocks
derived from PLL4 and PLL5.
Signed-off-by: Danny Nold <dannynold@freescale.com>
Diffstat (limited to 'arch/arm/mach-mx6/crm_regs.h')
| -rw-r--r-- | arch/arm/mach-mx6/crm_regs.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm/mach-mx6/crm_regs.h b/arch/arm/mach-mx6/crm_regs.h index 7f54cab160ac..354d28b3f2e7 100644 --- a/arch/arm/mach-mx6/crm_regs.h +++ b/arch/arm/mach-mx6/crm_regs.h @@ -47,6 +47,7 @@ #define PFD_480_BASE_ADDR (MXC_PLL_BASE + 0xF0) #define PFD_528_BASE_ADDR (MXC_PLL_BASE + 0x100) #define ANADIG_REG_CORE (MXC_PLL_BASE + 0x140) +#define ANA_MISC2_BASE_ADDR (MXC_PLL_BASE + 0x170) #define PLL_SETREG_OFFSET 0x4 #define PLL_CLRREG_OFFSET 0x8 @@ -81,6 +82,8 @@ /* PLL4_AUDIO PLL5_VIDEO defines. */ #define ANADIG_PLL_AV_DIV_SELECT_MASK (0x7F) #define ANADIG_PLL_AV_DIV_SELECT_OFFSET (0) +#define ANADIG_PLL_AV_TEST_DIV_SEL_MASK (0x180000) +#define ANADIG_PLL_AV_TEST_DIV_SEL_OFFSET (19) /* PLL6_MLB defines. */ #define ANADIG_PLL_MLB_LOCK (1 << 31) @@ -131,6 +134,10 @@ #define ANADIG_REG0_CORE_ADJUST_OFFSET 5 #define ANADIG_REG0_CORE_TARGET_OFFSET 0 +/* ANA MISC2 register defines */ +#define ANADIG_ANA_MISC2_CONTROL3_MASK 0xC0000000 +#define ANADIG_ANA_MISC2_CONTROL3_OFFSET 30 + #define MXC_CCM_BASE MX6_IO_ADDRESS(CCM_BASE_ADDR) /* CCM Register Offsets. */ #define MXC_CCM_CDCR_OFFSET 0x4C |