diff options
| author | Anson Huang <b20788@freescale.com> | 2012-06-13 20:20:01 +0800 |
|---|---|---|
| committer | Nitin Garg <nitin.garg@freescale.com> | 2014-06-03 21:53:55 -0500 |
| commit | 713009b776e581edde0da1aa15e9b1e6235815ef (patch) | |
| tree | 346bb42bcb7bd262ea1645b65558adb06fcbb8d1 /arch/arm/mach-mx6/crm_regs.h | |
| parent | 75f3b8048c32e976cd682274b02891262b88862c (diff) | |
ENGR00180919 [MX6]Update clock tree if BUS freq is changed
As DDR freq change is by modifying CCM register directly,
we need to update the clock tree as well, or the clock
tree will be broken. Also, we need to make sure the clock
rate counting is right.
Signed-off-by: Anson Huang <b20788@freescale.com>
Diffstat (limited to 'arch/arm/mach-mx6/crm_regs.h')
| -rw-r--r-- | arch/arm/mach-mx6/crm_regs.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/mach-mx6/crm_regs.h b/arch/arm/mach-mx6/crm_regs.h index 188dbaebd57f..52fd75db9eb0 100644 --- a/arch/arm/mach-mx6/crm_regs.h +++ b/arch/arm/mach-mx6/crm_regs.h @@ -76,6 +76,8 @@ /* PLL1_SYS defines */ #define ANADIG_PLL_SYS_DIV_SELECT_MASK (0x7F) #define ANADIG_PLL_SYS_DIV_SELECT_OFFSET (0) +#define ANADIG_PLL_SYS_BYPASS_MASK (0x10000) +#define ANADIG_PLL_SYS_BYPASS_OFFSET (16) /* PLL2_528 defines */ #define ANADIG_PLL_528_DIV_SELECT (1) |