diff options
| author | Richard Zhu <r65037@freescale.com> | 2011-07-05 15:03:16 +0800 |
|---|---|---|
| committer | Jason Liu <r64343@freescale.com> | 2012-07-20 13:14:19 +0800 |
| commit | ada490e53907f710a7829ace839479a987768905 (patch) | |
| tree | 47f2d4b44a3a6afb07932f5714e1643301e1213c /arch/arm/mach-mx6/crm_regs.h | |
| parent | 01b0b8aa2e0703cfca0befc3baa6c2151b673372 (diff) | |
ENGR00139241-2 mx6 sata: enable ahci sata module on mx6q
Eanble ahci sata on mx6q
Signed-off-by: Richard Zhu <r65037@freescale.com>
Diffstat (limited to 'arch/arm/mach-mx6/crm_regs.h')
| -rw-r--r-- | arch/arm/mach-mx6/crm_regs.h | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/arch/arm/mach-mx6/crm_regs.h b/arch/arm/mach-mx6/crm_regs.h index a0a6fc896a56..e436ccfc8baa 100644 --- a/arch/arm/mach-mx6/crm_regs.h +++ b/arch/arm/mach-mx6/crm_regs.h @@ -11,6 +11,23 @@ #ifndef __ARCH_ARM_MACH_MX6_CRM_REGS_H__ #define __ARCH_ARM_MACH_MX6_CRM_REGS_H__ +/* IOMUXC */ +#define MXC_IOMUXC_BASE MX6_IO_ADDRESS(IOMUXC_BASE_ADDR) +#define IOMUXC_GPR0 (MXC_IOMUXC_BASE + 0x00) +#define IOMUXC_GPR1 (MXC_IOMUXC_BASE + 0x04) +#define IOMUXC_GPR2 (MXC_IOMUXC_BASE + 0x08) +#define IOMUXC_GPR3 (MXC_IOMUXC_BASE + 0x0C) +#define IOMUXC_GPR4 (MXC_IOMUXC_BASE + 0x10) +#define IOMUXC_GPR5 (MXC_IOMUXC_BASE + 0x14) +#define IOMUXC_GPR6 (MXC_IOMUXC_BASE + 0x18) +#define IOMUXC_GPR7 (MXC_IOMUXC_BASE + 0x1C) +#define IOMUXC_GPR8 (MXC_IOMUXC_BASE + 0x20) +#define IOMUXC_GPR9 (MXC_IOMUXC_BASE + 0x24) +#define IOMUXC_GPR10 (MXC_IOMUXC_BASE + 0x28) +#define IOMUXC_GPR11 (MXC_IOMUXC_BASE + 0x2C) +#define IOMUXC_GPR12 (MXC_IOMUXC_BASE + 0x30) +#define IOMUXC_GPR13 (MXC_IOMUXC_BASE + 0x34) + /* PLLs */ #define MXC_PLL_BASE MX6_IO_ADDRESS(ANATOP_BASE_ADDR) #define PLL1_SYS_BASE_ADDR (MXC_PLL_BASE + 0x0) @@ -69,8 +86,12 @@ #define ANADIG_PLL_MLB_VDDA_DELAY_CFG_OFFSET (17) /* PLL8_ENET defines. */ +#define ANADIG_PLL_ENET_LOCK (1 << 31) #define ANADIG_PLL_ENET_EN_SATA (1 << 20) #define ANADIG_PLL_ENET_EN_PCIE (1 << 19) +#define ANADIG_PLL_ENET_BYPASS (1 << 16) +#define ANADIG_PLL_ENET_EN (1 << 13) +#define ANADIG_PLL_ENET_POWER_DOWN (1 << 12) #define ANADIG_PLL_ENET_DIV_SELECT_MASK (0x3) #define ANADIG_PLL_ENET_DIV_SELECT_OFFSET (0) |